Search

Joseph E. Palys

Examiner (ID: 14231)

Most Active Art Unit
2413
Art Unit(s)
2413, 2313, 2787, 2899, 2785
Total Applications
453
Issued Applications
351
Pending Applications
23
Abandoned Applications
79

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4026386 [patent_doc_number] => 05941994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Technique for sharing hot spare drives among multiple subsystems' [patent_app_type] => 1 [patent_app_number] => 8/577311 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3255 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941994.pdf [firstpage_image] =>[orig_patent_app_number] => 577311 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/577311
Technique for sharing hot spare drives among multiple subsystems Dec 21, 1995 Issued
Array ( [id] => 3674778 [patent_doc_number] => 05598420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Apparatus and method for generating a power signal for a power system from signals genenrated by a communication device' [patent_app_type] => 1 [patent_app_number] => 8/577063 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4304 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598420.pdf [firstpage_image] =>[orig_patent_app_number] => 577063 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/577063
Apparatus and method for generating a power signal for a power system from signals genenrated by a communication device Dec 21, 1995 Issued
Array ( [id] => 3802313 [patent_doc_number] => 05737517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Testing tools in an intelligent network system' [patent_app_type] => 1 [patent_app_number] => 8/577913 [patent_app_country] => US [patent_app_date] => 1995-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4577 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737517.pdf [firstpage_image] =>[orig_patent_app_number] => 577913 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/577913
Testing tools in an intelligent network system Dec 20, 1995 Issued
Array ( [id] => 3847443 [patent_doc_number] => 05740359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Program execution system having a plurality of program versions' [patent_app_type] => 1 [patent_app_number] => 8/580032 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3338 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740359.pdf [firstpage_image] =>[orig_patent_app_number] => 580032 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/580032
Program execution system having a plurality of program versions Dec 19, 1995 Issued
Array ( [id] => 3847361 [patent_doc_number] => 05740353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method and apparatus for creating a multiprocessor verification environment' [patent_app_type] => 1 [patent_app_number] => 8/572472 [patent_app_country] => US [patent_app_date] => 1995-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9008 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740353.pdf [firstpage_image] =>[orig_patent_app_number] => 572472 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/572472
Method and apparatus for creating a multiprocessor verification environment Dec 13, 1995 Issued
Array ( [id] => 3861695 [patent_doc_number] => 05720031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Method and apparatus for testing memory devices and displaying results of such tests' [patent_app_type] => 1 [patent_app_number] => 8/567069 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7989 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/720/05720031.pdf [firstpage_image] =>[orig_patent_app_number] => 567069 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/567069
Method and apparatus for testing memory devices and displaying results of such tests Dec 3, 1995 Issued
Array ( [id] => 3896578 [patent_doc_number] => 05805799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Data integrity and cross-check code with logical block address' [patent_app_type] => 1 [patent_app_number] => 8/566361 [patent_app_country] => US [patent_app_date] => 1995-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9925 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805799.pdf [firstpage_image] =>[orig_patent_app_number] => 566361 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/566361
Data integrity and cross-check code with logical block address Nov 30, 1995 Issued
Array ( [id] => 4069616 [patent_doc_number] => 05864657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Main memory system and checkpointing protocol for fault-tolerant computer system' [patent_app_type] => 1 [patent_app_number] => 8/564021 [patent_app_country] => US [patent_app_date] => 1995-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864657.pdf [firstpage_image] =>[orig_patent_app_number] => 564021 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/564021
Main memory system and checkpointing protocol for fault-tolerant computer system Nov 28, 1995 Issued
Array ( [id] => 3707108 [patent_doc_number] => 05680536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Dual motherboard computer system' [patent_app_type] => 1 [patent_app_number] => 8/563747 [patent_app_country] => US [patent_app_date] => 1995-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3592 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680536.pdf [firstpage_image] =>[orig_patent_app_number] => 563747 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/563747
Dual motherboard computer system Nov 28, 1995 Issued
Array ( [id] => 3910742 [patent_doc_number] => 05835776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions' [patent_app_type] => 1 [patent_app_number] => 8/560089 [patent_app_country] => US [patent_app_date] => 1995-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7212 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835776.pdf [firstpage_image] =>[orig_patent_app_number] => 560089 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/560089
Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions Nov 16, 1995 Issued
Array ( [id] => 3715820 [patent_doc_number] => 05675726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Flexible parity generation circuit' [patent_app_type] => 1 [patent_app_number] => 8/555331 [patent_app_country] => US [patent_app_date] => 1995-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5401 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675726.pdf [firstpage_image] =>[orig_patent_app_number] => 555331 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/555331
Flexible parity generation circuit Nov 7, 1995 Issued
Array ( [id] => 3563828 [patent_doc_number] => 05572665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Semiconductor integrated circuit for developing a system using a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/551355 [patent_app_country] => US [patent_app_date] => 1995-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4318 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572665.pdf [firstpage_image] =>[orig_patent_app_number] => 551355 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/551355
Semiconductor integrated circuit for developing a system using a microprocessor Oct 31, 1995 Issued
08/549502 PASSWORD PROTECTION FOR REMOVABLE HARD DRIVE Oct 26, 1995 Abandoned
08/549292 PRESERVATION OF DATA INTEGRITY IN A RAID STORAGE DEVICE Oct 26, 1995 Abandoned
08/543835 METHOD FOR DOWNLOADING SPECIAL CODE FROM A COMPUTER TO A HARD COPY APPARATUS Oct 15, 1995 Abandoned
08/543011 READ CHECKING FOR DRIVE REBUILD Oct 12, 1995 Abandoned
Array ( [id] => 3750511 [patent_doc_number] => 05699511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'System and method for dynamically varying low level file system operation timeout parameters in network systems of variable bandwidth' [patent_app_type] => 1 [patent_app_number] => 8/540431 [patent_app_country] => US [patent_app_date] => 1995-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3318 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699511.pdf [firstpage_image] =>[orig_patent_app_number] => 540431 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540431
System and method for dynamically varying low level file system operation timeout parameters in network systems of variable bandwidth Oct 9, 1995 Issued
Array ( [id] => 3735549 [patent_doc_number] => 05673384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Dual disk lock arbitration between equal sized partition of a cluster' [patent_app_type] => 1 [patent_app_number] => 8/540381 [patent_app_country] => US [patent_app_date] => 1995-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2970 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673384.pdf [firstpage_image] =>[orig_patent_app_number] => 540381 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540381
Dual disk lock arbitration between equal sized partition of a cluster Oct 5, 1995 Issued
Array ( [id] => 3871484 [patent_doc_number] => 05768502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Error correcting apparatus for detecting and correcting errors in data accessed from a storage medium' [patent_app_type] => 1 [patent_app_number] => 8/539884 [patent_app_country] => US [patent_app_date] => 1995-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8155 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768502.pdf [firstpage_image] =>[orig_patent_app_number] => 539884 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539884
Error correcting apparatus for detecting and correcting errors in data accessed from a storage medium Oct 5, 1995 Issued
Array ( [id] => 3523768 [patent_doc_number] => 05564016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Method for controlling access to a computer resource based on a timing policy' [patent_app_type] => 1 [patent_app_number] => 8/536603 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3631 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/564/05564016.pdf [firstpage_image] =>[orig_patent_app_number] => 536603 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536603
Method for controlling access to a computer resource based on a timing policy Sep 28, 1995 Issued
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