Search

Joseph J. Lauture

Examiner (ID: 11027, Phone: (571)272-1805 , Office: P/2845 )

Most Active Art Unit
2845
Art Unit(s)
2845, 2819
Total Applications
2179
Issued Applications
2043
Pending Applications
96
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20696622 [patent_doc_number] => 20260128035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-07 [patent_title] => SYSTEMS AND METHODS FOR AUDIO TRANSPORT [patent_app_type] => utility [patent_app_number] => 19/440513 [patent_app_country] => US [patent_app_date] => 2026-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19440513 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/440513
SYSTEMS AND METHODS FOR AUDIO TRANSPORT Jan 4, 2026 Pending
Array ( [id] => 20617914 [patent_doc_number] => 20260088016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => SYSTEMS AND METHODS FOR DATA TRANSMISSION [patent_app_type] => utility [patent_app_number] => 19/406310 [patent_app_country] => US [patent_app_date] => 2025-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19406310 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/406310
SYSTEMS AND METHODS FOR DATA TRANSMISSION Dec 1, 2025 Pending
Array ( [id] => 20382522 [patent_doc_number] => 20250365015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => ARITHMETIC ENCODER FOR ARITHMETICALLY ENCODING AND ARITHMETIC DECODER FOR ARITHMETICALLY DECODING A SEQUENCE OF INFORMATION VALUES, METHODS FOR ARITHMETICALLY ENCODING AND DECODING A SEQUENCE OF INFORMATION VALUES AND COMPUTER PROGRAM FOR IMPLEMENTING THESE METHODS [patent_app_type] => utility [patent_app_number] => 19/293159 [patent_app_country] => US [patent_app_date] => 2025-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19293159 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/293159
ARITHMETIC ENCODER FOR ARITHMETICALLY ENCODING AND ARITHMETIC DECODER FOR ARITHMETICALLY DECODING A SEQUENCE OF INFORMATION VALUES, METHODS FOR ARITHMETICALLY ENCODING AND DECODING A SEQUENCE OF INFORMATION VALUES AND COMPUTER PROGRAM FOR IMPLEMENTING THESE METHODS Aug 6, 2025 Pending
Array ( [id] => 20382521 [patent_doc_number] => 20250365014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => ARITHMETIC ENCODER FOR ARITHMETICALLY ENCODING AND ARITHMETIC DECODER FOR ARITHMETICALLY DECODING A SEQUENCE OF INFORMATION VALUES, METHODS FOR ARITHMETICALLY ENCODING AND DECODING A SEQUENCE OF INFORMATION VALUES AND COMPUTER PROGRAM FOR IMPLEMENTING THESE METHODS [patent_app_type] => utility [patent_app_number] => 19/293121 [patent_app_country] => US [patent_app_date] => 2025-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19293121 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/293121
ARITHMETIC ENCODER FOR ARITHMETICALLY ENCODING AND ARITHMETIC DECODER FOR ARITHMETICALLY DECODING A SEQUENCE OF INFORMATION VALUES, METHODS FOR ARITHMETICALLY ENCODING AND DECODING A SEQUENCE OF INFORMATION VALUES AND COMPUTER PROGRAM FOR IMPLEMENTING THESE METHODS Aug 6, 2025 Pending
Array ( [id] => 20690842 [patent_doc_number] => 12621005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Arithmetic encoder for arithmetically encoding and arithmetic decoder for arithmetically decoding a sequence of information values, methods for arithmetically encoding and decoding a sequence of information values and computer program for implementing these methods [patent_app_type] => utility [patent_app_number] => 19/293189 [patent_app_country] => US [patent_app_date] => 2025-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 21793 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19293189 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/293189
Arithmetic encoder for arithmetically encoding and arithmetic decoder for arithmetically decoding a sequence of information values, methods for arithmetically encoding and decoding a sequence of information values and computer program for implementing these methods Aug 6, 2025 Issued
Array ( [id] => 20474630 [patent_doc_number] => 20260016851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => HIGH-SPEED DELTA SIGMA MODULATORS [patent_app_type] => utility [patent_app_number] => 19/033536 [patent_app_country] => US [patent_app_date] => 2025-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19033536 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/033536
HIGH-SPEED DELTA SIGMA MODULATORS Jan 21, 2025 Pending
Array ( [id] => 20125000 [patent_doc_number] => 20250240031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => MACHINE LEARNING ACCELERATOR, COMPUTING DEVICE INCLUDING MACHINE LEARNING ACCELERATOR, AND METHOD OF LOADING DATA TO MACHINE LEARNING ACCELERATOR [patent_app_type] => utility [patent_app_number] => 19/018375 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19018375 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/018375
MACHINE LEARNING ACCELERATOR, COMPUTING DEVICE INCLUDING MACHINE LEARNING ACCELERATOR, AND METHOD OF LOADING DATA TO MACHINE LEARNING ACCELERATOR Jan 12, 2025 Pending
Array ( [id] => 20064272 [patent_doc_number] => 20250202494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SELF-CALIBRATING DIGITAL TO ANALOG CONVERTER [patent_app_type] => utility [patent_app_number] => 18/965059 [patent_app_country] => US [patent_app_date] => 2024-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18965059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/965059
SELF-CALIBRATING DIGITAL TO ANALOG CONVERTER Dec 1, 2024 Pending
Array ( [id] => 20476866 [patent_doc_number] => 20260019087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => SELF-CALIBRATION DIGITAL-TO-ANALOG CONVERTER AND CALIBRATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/965119 [patent_app_country] => US [patent_app_date] => 2024-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18965119 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/965119
SELF-CALIBRATION DIGITAL-TO-ANALOG CONVERTER AND CALIBRATION METHOD THEREOF Dec 1, 2024 Pending
Array ( [id] => 19833888 [patent_doc_number] => 20250085674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => SCALABLE ANALOG PIM MODULE, METHOD OF CONTROLLING ANALOG PIM, SIGNAL PROCESSING CIRCUIT, AND SENSOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/957653 [patent_app_country] => US [patent_app_date] => 2024-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18957653 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/957653
SCALABLE ANALOG PIM MODULE, METHOD OF CONTROLLING ANALOG PIM, SIGNAL PROCESSING CIRCUIT, AND SENSOR DEVICE Nov 21, 2024 Pending
Array ( [id] => 20618727 [patent_doc_number] => 20260088831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => Compression Metadata Value Induced Read and Write Operation Conservation [patent_app_type] => utility [patent_app_number] => 18/949366 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18949366 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/949366
Compression Metadata Value Induced Read and Write Operation Conservation Nov 14, 2024 Pending
Array ( [id] => 20725950 [patent_doc_number] => 20260142670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-21 [patent_title] => SWITCH-CAPACITOR FILTER FOR RECEIVER BASEBAND ANTI-ALIASING SIGNAL FILTERING [patent_app_type] => utility [patent_app_number] => 18/949633 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18949633 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/949633
SWITCH-CAPACITOR FILTER FOR RECEIVER BASEBAND ANTI-ALIASING SIGNAL FILTERING Nov 14, 2024 Pending
Array ( [id] => 20089710 [patent_doc_number] => 20250219646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => ANALOG-TO-DIGITAL CONVERTER CIRCUIT AND METHOD AND DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/944726 [patent_app_country] => US [patent_app_date] => 2024-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18944726 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/944726
ANALOG-TO-DIGITAL CONVERTER CIRCUIT AND METHOD AND DEVICE USING THE SAME Nov 11, 2024 Pending
Array ( [id] => 20733490 [patent_doc_number] => 12640752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Multiplying digital-to-analog converter [patent_app_type] => utility [patent_app_number] => 18/940923 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18940923 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/940923
Multiplying digital-to-analog converter Nov 7, 2024 Issued
Array ( [id] => 20682795 [patent_doc_number] => 20260121624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => METHODS AND APPARATUS TO IMPLEMENT DELAY LINES AND ANALOG TO DIGITAL CONVERTERS [patent_app_type] => utility [patent_app_number] => 18/932058 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932058
METHODS AND APPARATUS TO IMPLEMENT DELAY LINES AND ANALOG TO DIGITAL CONVERTERS Oct 29, 2024 Pending
Array ( [id] => 20790076 [patent_doc_number] => 12663991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Data interface device of display apparatus [patent_app_type] => utility [patent_app_number] => 18/920050 [patent_app_country] => US [patent_app_date] => 2024-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 1367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18920050 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/920050
Data interface device of display apparatus Oct 17, 2024 Issued
Array ( [id] => 20654605 [patent_doc_number] => 20260106630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => SYSTEM AND METHOD FOR SEARCHING DATA VIA PACKED-DECIMAL CONVERSION WITHIN A STANDALONE MAINFRAME CLIENT [patent_app_type] => utility [patent_app_number] => 18/917818 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917818 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/917818
SYSTEM AND METHOD FOR SEARCHING DATA VIA PACKED-DECIMAL CONVERSION WITHIN A STANDALONE MAINFRAME CLIENT Oct 15, 2024 Pending
Array ( [id] => 20029575 [patent_doc_number] => 20250167797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => DTC LINEARIZATION VIA MISMATCH-NOISE CANCELLATION FOR DIGITAL FRACTIONAL-N PLLS [patent_app_type] => utility [patent_app_number] => 18/911901 [patent_app_country] => US [patent_app_date] => 2024-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18911901 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/911901
DTC LINEARIZATION VIA MISMATCH-NOISE CANCELLATION FOR DIGITAL FRACTIONAL-N PLLS Oct 9, 2024 Pending
Array ( [id] => 19727683 [patent_doc_number] => 20250030434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => SYSTEMS AND METHODS OF SIGNED CONVERSION [patent_app_type] => utility [patent_app_number] => 18/910485 [patent_app_country] => US [patent_app_date] => 2024-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18910485 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/910485
SYSTEMS AND METHODS OF SIGNED CONVERSION Oct 8, 2024 Pending
Array ( [id] => 20140060 [patent_doc_number] => 20250247104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND ANALOG-TO-DIGITAL CONVERSION METHOD THEREOF COMBINING SUCCESSIVE APPROXIMATION PROCEDURE AND INITIAL VOLTAGE SCANNING PROCEDURE [patent_app_type] => utility [patent_app_number] => 18/910119 [patent_app_country] => US [patent_app_date] => 2024-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18910119 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/910119
ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND ANALOG-TO-DIGITAL CONVERSION METHOD THEREOF COMBINING SUCCESSIVE APPROXIMATION PROCEDURE AND INITIAL VOLTAGE SCANNING PROCEDURE Oct 8, 2024 Issued
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