Joseph L. Williams

Array ( [id] => 8068279 [patent_doc_number] => 20110242891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'OPERATION METHODS FOR MEMORY CELL AND ARRAY FOR REDUCING PUNCH THROUGH LEAKAGE' [patent_app_type] => utility [patent_app_number] => 13/159410 [patent_app_country] => US [patent_app_date] => 2011-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 18814 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20110242891.pdf [firstpage_image] =>[orig_patent_app_number] => 13159410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8284256 [patent_doc_number] => 08218364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Operation methods for memory cell and array for reducing punch through leakage' [patent_app_type] => utility [patent_app_number] => 13/159413 [patent_app_country] => US [patent_app_date] => 2011-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 18812 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13159413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7485121 [patent_doc_number] => 20110235417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'NAND FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 13/154522 [patent_app_country] => US [patent_app_date] => 2011-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8165 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20110235417.pdf [firstpage_image] =>[orig_patent_app_number] => 13154522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6013211 [patent_doc_number] => 20110222345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations' [patent_app_type] => utility [patent_app_number] => 13/114481 [patent_app_country] => US [patent_app_date] => 2011-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 16932 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20110222345.pdf [firstpage_image] =>[orig_patent_app_number] => 13114481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8827608 [patent_doc_number] => 20130128653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'RESISTIVE RADOM ACCESS MEMORY DEVICE, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/701626 [patent_app_country] => US [patent_app_date] => 2011-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4643 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13701626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7754050 [patent_doc_number] => 08111534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Rank select using a global select pin' [patent_app_type] => utility [patent_app_number] => 13/109852 [patent_app_country] => US [patent_app_date] => 2011-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/111/08111534.pdf [firstpage_image] =>[orig_patent_app_number] => 13109852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8250876 [patent_doc_number] => 20120155203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND SYSTEM OF TESTING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/104262 [patent_app_country] => US [patent_app_date] => 2011-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3489 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20120155203.pdf [firstpage_image] =>[orig_patent_app_number] => 13104262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8877292 [patent_doc_number] => 08472265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Repairing circuit for memory circuit and method thereof and memory circuit using the same' [patent_app_type] => utility [patent_app_number] => 13/104038 [patent_app_country] => US [patent_app_date] => 2011-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8907 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13104038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8702708 [patent_doc_number] => 08395936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Using channel-to-channel coupling to compensate floating gate-to-floating gate coupling in programming of non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/103854 [patent_app_country] => US [patent_app_date] => 2011-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 14004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13103854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8482050 [patent_doc_number] => 20120281457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'Data Dependent SRAM Write Assist' [patent_app_type] => utility [patent_app_number] => 13/101436 [patent_app_country] => US [patent_app_date] => 2011-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2286 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13101436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8809104 [patent_doc_number] => 08446764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Control voltage generation circuit and non-volatile memory device including the same' [patent_app_type] => utility [patent_app_number] => 13/101522 [patent_app_country] => US [patent_app_date] => 2011-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6553 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13101522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9168210 [patent_doc_number] => 08593894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Semiconductor memory device having fuse elements programmed by irradiation with laser beam' [patent_app_type] => utility [patent_app_number] => 13/100736 [patent_app_country] => US [patent_app_date] => 2011-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6131 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13100736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9185417 [patent_doc_number] => 08625363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/100906 [patent_app_country] => US [patent_app_date] => 2011-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 8053 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13100906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8761762 [patent_doc_number] => 08422292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Nonvolatile memory device and program method thereof' [patent_app_type] => utility [patent_app_number] => 13/100134 [patent_app_country] => US [patent_app_date] => 2011-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13100134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8106501 [patent_doc_number] => 08154902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Bit line decoder architecture for NOR-type memory array' [patent_app_type] => utility [patent_app_number] => 13/099792 [patent_app_country] => US [patent_app_date] => 2011-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 7478 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/154/08154902.pdf [firstpage_image] =>[orig_patent_app_number] => 13099792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8482053 [patent_doc_number] => 20120281460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'NONCONTACT WRITING OF NANOMETER SCALE MAGNETIC BITS USING HEAT FLOW INDUCED SPIN TORQUE EFFECT' [patent_app_type] => utility [patent_app_number] => 13/100026 [patent_app_country] => US [patent_app_date] => 2011-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8366 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13100026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8482060 [patent_doc_number] => 20120281467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'MAGNONIC MAGNETIC RANDOM ACCESS MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/100032 [patent_app_country] => US [patent_app_date] => 2011-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7370 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13100032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8167412 [patent_doc_number] => 08174885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'High speed operation method for twin MONOS metal bit array' [patent_app_type] => utility [patent_app_number] => 13/068066 [patent_app_country] => US [patent_app_date] => 2011-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 38 [patent_no_of_words] => 7505 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174885.pdf [firstpage_image] =>[orig_patent_app_number] => 13068066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6163454 [patent_doc_number] => 20110194351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'SOURCE SIDE ASYMMETRICAL PRECHARGE PROGRAMMING SCHEME' [patent_app_type] => utility [patent_app_number] => 13/091479 [patent_app_country] => US [patent_app_date] => 2011-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11937 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20110194351.pdf [firstpage_image] =>[orig_patent_app_number] => 13091479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8334377 [patent_doc_number] => 20120201085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'LOW POWER MEMORY CONTROL CIRCUITS AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/089486 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11529 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13089486 [rel_patent_id] =>[rel_patent_doc_number] =>)