
Joseph P. Hirl
Supervisory Patent Examiner (ID: 3363, Phone: (571)272-3685 , Office: P/2435 )
| Most Active Art Unit | 2129 |
| Art Unit(s) | 2435, 2426, 2121, 2129 |
| Total Applications | 524 |
| Issued Applications | 377 |
| Pending Applications | 22 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9754534
[patent_doc_number] => 20140285234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-25
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/217628
[patent_app_country] => US
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Array
(
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[patent_doc_number] => 09166599
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[patent_kind] => B1
[patent_issue_date] => 2015-10-20
[patent_title] => 'Methods and apparatus for building bus interconnection networks using programmable interconnection resources'
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[patent_app_number] => 14/212667
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Array
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[patent_title] => 'SHARING HARDWARE RESOURCES BETWEEN D-PHY AND N-FACTORIAL TERMINATION NETWORKS'
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[patent_app_number] => 14/210246
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/210246 | Sharing hardware resources between D-PHY and N-factorial termination networks | Mar 12, 2014 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/200061 | Semiconductor devices and structures | Mar 6, 2014 | Issued |
Array
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Array
(
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[patent_title] => 'Integrated circuit floorplans'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/198524 | Integrated circuit floorplans | Mar 4, 2014 | Issued |
Array
(
[id] => 9730595
[patent_doc_number] => 20140266301
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[patent_issue_date] => 2014-09-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/198355 | Programmable logic device | Mar 4, 2014 | Issued |
Array
(
[id] => 9688216
[patent_doc_number] => 20140244981
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[patent_issue_date] => 2014-08-28
[patent_title] => 'PROCESSOR AND CONTROL METHOD FOR PROCESSOR'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/188157 | Processor and control method for processor | Feb 23, 2014 | Issued |
Array
(
[id] => 10003379
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[patent_title] => 'Circuits for and methods of providing isolation in an integrated circuit'
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Array
(
[id] => 10899018
[patent_doc_number] => 08922242
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[patent_issue_date] => 2014-12-30
[patent_title] => 'Single event upset mitigation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/185587 | Single event upset mitigation | Feb 19, 2014 | Issued |
Array
(
[id] => 10342435
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Array
(
[id] => 9558518
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Array
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Array
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Array
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Array
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Array
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Array
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