
Joseph R. Burwell
Examiner (ID: 1911, Phone: (571)270-5608 , Office: P/2143 )
| Most Active Art Unit | 2143 |
| Art Unit(s) | 2412, 2178, 2143, 2772, 2301, 2776 |
| Total Applications | 379 |
| Issued Applications | 241 |
| Pending Applications | 18 |
| Abandoned Applications | 121 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1156261
[patent_doc_number] => 06762111
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[patent_title] => 'Method of manufacturing a semiconductor device'
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[pdf_file] => patents/06/762/06762111.pdf
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Array
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[patent_title] => 'Method for manufacturing a semiconductor device'
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Array
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Array
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[patent_title] => 'Method to improve etching of resist protective oxide (RPO) to prevent photo-resist peeling'
[patent_app_type] => utility
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Array
(
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[patent_issue_date] => 2004-09-28
[patent_title] => 'Solution for ruthenium chemical mechanical planarization'
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Array
(
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[patent_issue_date] => 2005-01-11
[patent_title] => 'Wafer treatment method for protecting fuse box of semiconductor chip'
[patent_app_type] => utility
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Array
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Array
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[patent_issue_date] => 2004-09-21
[patent_title] => 'Method of fabricating semiconductor memory device and semiconductor memory device driver'
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Array
(
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Array
(
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[patent_title] => 'Method of trench sidewall enhancement'
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[patent_app_number] => 10/279142
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Array
(
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Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/233432 | Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device | Sep 3, 2002 | Issued |