Search

Joseph R. Burwell

Examiner (ID: 1911, Phone: (571)270-5608 , Office: P/2143 )

Most Active Art Unit
2143
Art Unit(s)
2412, 2178, 2143, 2772, 2301, 2776
Total Applications
379
Issued Applications
241
Pending Applications
18
Abandoned Applications
121

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1156261 [patent_doc_number] => 06762111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/301702 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 6807 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762111.pdf [firstpage_image] =>[orig_patent_app_number] => 10301702 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301702
Method of manufacturing a semiconductor device Nov 21, 2002 Issued
Array ( [id] => 6816067 [patent_doc_number] => 20030067025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/295457 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1812 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20030067025.pdf [firstpage_image] =>[orig_patent_app_number] => 10295457 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/295457
Method for manufacturing a semiconductor device Nov 14, 2002 Abandoned
Array ( [id] => 7365410 [patent_doc_number] => 20040092132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Atomic layer deposition methods' [patent_app_type] => new [patent_app_number] => 10/293072 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5470 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092132.pdf [firstpage_image] =>[orig_patent_app_number] => 10293072 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/293072
Atomic layer deposition methods Nov 11, 2002 Issued
Array ( [id] => 757623 [patent_doc_number] => 07015089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Method to improve etching of resist protective oxide (RPO) to prevent photo-resist peeling' [patent_app_type] => utility [patent_app_number] => 10/289761 [patent_app_country] => US [patent_app_date] => 2002-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2558 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015089.pdf [firstpage_image] =>[orig_patent_app_number] => 10289761 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/289761
Method to improve etching of resist protective oxide (RPO) to prevent photo-resist peeling Nov 6, 2002 Issued
Array ( [id] => 1119863 [patent_doc_number] => 06797624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Solution for ruthenium chemical mechanical planarization' [patent_app_type] => B2 [patent_app_number] => 10/288058 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1575 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797624.pdf [firstpage_image] =>[orig_patent_app_number] => 10288058 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/288058
Solution for ruthenium chemical mechanical planarization Nov 4, 2002 Issued
Array ( [id] => 1071842 [patent_doc_number] => 06841425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Wafer treatment method for protecting fuse box of semiconductor chip' [patent_app_type] => utility [patent_app_number] => 10/282741 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2468 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841425.pdf [firstpage_image] =>[orig_patent_app_number] => 10282741 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282741
Wafer treatment method for protecting fuse box of semiconductor chip Oct 27, 2002 Issued
Array ( [id] => 1285045 [patent_doc_number] => 06638815 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Formation of self-aligned vertical connector' [patent_app_type] => B1 [patent_app_number] => 10/280971 [patent_app_country] => US [patent_app_date] => 2002-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2721 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/638/06638815.pdf [firstpage_image] =>[orig_patent_app_number] => 10280971 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/280971
Formation of self-aligned vertical connector Oct 24, 2002 Issued
Array ( [id] => 1123363 [patent_doc_number] => 06794248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Method of fabricating semiconductor memory device and semiconductor memory device driver' [patent_app_type] => B2 [patent_app_number] => 10/279981 [patent_app_country] => US [patent_app_date] => 2002-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3999 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794248.pdf [firstpage_image] =>[orig_patent_app_number] => 10279981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279981
Method of fabricating semiconductor memory device and semiconductor memory device driver Oct 24, 2002 Issued
Array ( [id] => 7383274 [patent_doc_number] => 20040082136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Breakdown voltage adjustment for bipolar transistors' [patent_app_type] => new [patent_app_number] => 10/280931 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7611 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082136.pdf [firstpage_image] =>[orig_patent_app_number] => 10280931 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/280931
Breakdown voltage adjustment for bipolar transistors Oct 23, 2002 Issued
Array ( [id] => 1216403 [patent_doc_number] => 06706586 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Method of trench sidewall enhancement' [patent_app_type] => B1 [patent_app_number] => 10/279142 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 3737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/706/06706586.pdf [firstpage_image] =>[orig_patent_app_number] => 10279142 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279142
Method of trench sidewall enhancement Oct 22, 2002 Issued
Array ( [id] => 6690882 [patent_doc_number] => 20030038314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/277891 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2694 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20030038314.pdf [firstpage_image] =>[orig_patent_app_number] => 10277891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/277891
Semiconductor device and method of manufacturing the same Oct 22, 2002 Abandoned
Array ( [id] => 1216377 [patent_doc_number] => 06706571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Method for forming multiple structures in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/274951 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2828 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/706/06706571.pdf [firstpage_image] =>[orig_patent_app_number] => 10274951 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/274951
Method for forming multiple structures in a semiconductor device Oct 21, 2002 Issued
Array ( [id] => 1138226 [patent_doc_number] => 06780715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Method for fabricating merged dram with logic semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/274052 [patent_app_country] => US [patent_app_date] => 2002-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 5521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780715.pdf [firstpage_image] =>[orig_patent_app_number] => 10274052 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/274052
Method for fabricating merged dram with logic semiconductor device Oct 20, 2002 Issued
Array ( [id] => 7167163 [patent_doc_number] => 20040077122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Process and device using self-organizable polymer' [patent_app_type] => new [patent_app_number] => 10/273901 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20040077122.pdf [firstpage_image] =>[orig_patent_app_number] => 10273901 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/273901
Process using self-organizable polymer Oct 16, 2002 Issued
Array ( [id] => 6657221 [patent_doc_number] => 20030077870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Method of reducing device parasitic capacitance using underneath crystallographically selective wet etching' [patent_app_type] => new [patent_app_number] => 10/271246 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1716 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20030077870.pdf [firstpage_image] =>[orig_patent_app_number] => 10271246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/271246
Method of reducing device parasitic capacitance using underneath crystallographically selective wet etching Oct 14, 2002 Issued
Array ( [id] => 1390908 [patent_doc_number] => 06552382 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Scalable vertical DRAM cell structure and its manufacturing methods' [patent_app_type] => B1 [patent_app_number] => 10/262201 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 8075 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 525 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552382.pdf [firstpage_image] =>[orig_patent_app_number] => 10262201 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/262201
Scalable vertical DRAM cell structure and its manufacturing methods Sep 29, 2002 Issued
Array ( [id] => 6678574 [patent_doc_number] => 20030228715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Active matrix backplane for controlling controlled elements and method of manufacture thereof' [patent_app_type] => new [patent_app_number] => 10/255972 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7561 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20030228715.pdf [firstpage_image] =>[orig_patent_app_number] => 10255972 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/255972
Active matrix backplane for controlling controlled elements and method of manufacture thereof Sep 25, 2002 Issued
Array ( [id] => 7280934 [patent_doc_number] => 20040063311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Structure of thin film transistor and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/259137 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2321 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20040063311.pdf [firstpage_image] =>[orig_patent_app_number] => 10259137 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/259137
Structure of thin film transistor and manufacturing method thereof Sep 25, 2002 Abandoned
Array ( [id] => 6720947 [patent_doc_number] => 20030054636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Method for manufacturing a semiconductor device and method for processing substrate' [patent_app_type] => new [patent_app_number] => 10/234842 [patent_app_country] => US [patent_app_date] => 2002-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4291 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054636.pdf [firstpage_image] =>[orig_patent_app_number] => 10234842 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/234842
Method for manufacturing a semiconductor device and method for processing substrate Sep 4, 2002 Abandoned
Array ( [id] => 1119819 [patent_doc_number] => 06797609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device' [patent_app_type] => B2 [patent_app_number] => 10/233432 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 96 [patent_no_of_words] => 19127 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797609.pdf [firstpage_image] =>[orig_patent_app_number] => 10233432 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233432
Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device Sep 3, 2002 Issued
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