Joseph S. Herrmann

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Array ( [id] => 20395283 [patent_doc_number] => 20250370758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => MULTI-CORE PROCESSOR, OPERATING METHOD, AND INSTRUCTIONS THEREFOR [patent_app_type] => utility [patent_app_number] => 18/964333 [patent_app_country] => US [patent_app_date] => 2024-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18964333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20027035 [patent_doc_number] => 20250165257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => LIGHTWEIGHT OUT OF ORDER SCHEDULER FOR PROCESSING UNITS [patent_app_type] => utility [patent_app_number] => 18/950479 [patent_app_country] => US [patent_app_date] => 2024-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18950479 [rel_patent_id] =>[rel_patent_doc_number] =>)

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