Joseph S. Herrmann

Array ( [id] => 16431394 [patent_doc_number] => 10831476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Compare and delay instructions [patent_app_type] => utility [patent_app_number] => 16/154231 [patent_app_country] => US [patent_app_date] => 2018-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 15840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18720127 [patent_doc_number] => 11797473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Accelerator architecture on a programmable platform [patent_app_type] => utility [patent_app_number] => 16/154517 [patent_app_country] => US [patent_app_date] => 2018-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 5614 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13992089 [patent_doc_number] => 20190065202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => POINTER-SIZE CONTROLLED INSTRUCTION PROCESSING [patent_app_type] => utility [patent_app_number] => 16/119448 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13497173 [patent_doc_number] => 20180300129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => CONDITIONAL TRANSACTION END INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/018343 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16018343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15870609 [patent_doc_number] => 20200142708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => Parallel Information Processing on Multi-Core Computing Platforms [patent_app_type] => utility [patent_app_number] => 16/622482 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16622482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13845529 [patent_doc_number] => 20190026249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => COMPUTATIONAL ARRAY MICROPROCESSOR SYSTEM USING NON-CONSECUTIVE DATA FORMATTING [patent_app_type] => utility [patent_app_number] => 15/920173 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17557812 [patent_doc_number] => 11314516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Issuing instructions based on resource conflict constraints in microprocessor [patent_app_type] => utility [patent_app_number] => 15/875611 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6366 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15875611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14585617 [patent_doc_number] => 20190220417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => Context Switch Optimization [patent_app_type] => utility [patent_app_number] => 15/874624 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14506317 [patent_doc_number] => 20190196813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => APPARATUS AND METHOD FOR MULTIPLYING, SUMMING, AND ACCUMULATING SETS OF PACKED BYTES [patent_app_type] => utility [patent_app_number] => 15/850499 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12800 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16772695 [patent_doc_number] => 10983799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-20 [patent_title] => Selection of instructions to issue in a processor [patent_app_type] => utility [patent_app_number] => 15/847552 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13525965 [patent_doc_number] => 20180314525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => INDIRECT TARGET TAGGED GEOMETRIC BRANCH PREDICTION USING A SET OF TARGET ADDRESS PATTERN DATA [patent_app_type] => utility [patent_app_number] => 15/844898 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 727 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15919415 [patent_doc_number] => 10656946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Predicting a table of contents pointer value responsive to branching to a subroutine [patent_app_type] => utility [patent_app_number] => 15/819420 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 44 [patent_no_of_words] => 16747 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12262494 [patent_doc_number] => 20180081689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'APPARATUS AND METHOD OF IMPROVED EXTRACT INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/809818 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 23165 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17515637 [patent_doc_number] => 11294787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Apparatus and method for controlling assertion of a trigger signal to processing circuitry [patent_app_type] => utility [patent_app_number] => 16/321503 [patent_app_country] => US [patent_app_date] => 2017-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8347 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16321503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14472699 [patent_doc_number] => 20190187994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SEQUENCE VERIFICATION [patent_app_type] => utility [patent_app_number] => 16/322983 [patent_app_country] => US [patent_app_date] => 2017-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16322983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12032702 [patent_doc_number] => 20170322802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'Performing Rounding Operations Responsive To An Instruction' [patent_app_type] => utility [patent_app_number] => 15/661190 [patent_app_country] => US [patent_app_date] => 2017-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5242 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15661190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12032705 [patent_doc_number] => 20170322804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'Performing Rounding Operations Responsive To An Instruction' [patent_app_type] => utility [patent_app_number] => 15/661211 [patent_app_country] => US [patent_app_date] => 2017-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5239 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15661211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12032704 [patent_doc_number] => 20170322803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'Performing Rounding Operations Responsive To An Instruction' [patent_app_type] => utility [patent_app_number] => 15/661199 [patent_app_country] => US [patent_app_date] => 2017-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5239 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15661199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14614671 [patent_doc_number] => 10360036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Cracked execution of move-to-FPSCR instructions [patent_app_type] => utility [patent_app_number] => 15/648247 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13782519 [patent_doc_number] => 20190004798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => STREAMING ENGINE WITH EARLY EXIT FROM LOOP LEVELS SUPPORTING EARLY EXIT LOOPS AND IRREGULAR LOOPS [patent_app_type] => utility [patent_app_number] => 15/636669 [patent_app_country] => US [patent_app_date] => 2017-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15636669 [rel_patent_id] =>[rel_patent_doc_number] =>)