Search

Joseph S. Herrmann

Examiner (ID: 821, Phone: (571)270-3291 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
572
Issued Applications
336
Pending Applications
66
Abandoned Applications
183

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13568979 [patent_doc_number] => 20180336037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => MULTI-LEVEL HISTORY BUFFER FOR TRANSACTION MEMORY IN A MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 15/597394 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/597394
Multi-level history buffer for transaction memory in a microprocessor May 16, 2017 Issued
Array ( [id] => 13568973 [patent_doc_number] => 20180336034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => NEAR MEMORY COMPUTING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 15/597757 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597757 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/597757
NEAR MEMORY COMPUTING ARCHITECTURE May 16, 2017 Abandoned
Array ( [id] => 14426975 [patent_doc_number] => 10318291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Providing vector horizontal compare functionality within a vector register [patent_app_type] => utility [patent_app_number] => 15/585505 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 16654 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585505 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/585505
Providing vector horizontal compare functionality within a vector register May 2, 2017 Issued
Array ( [id] => 16787976 [patent_doc_number] => 10990409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Control flow mechanism for execution of graphics processor instructions using active channel packing [patent_app_type] => utility [patent_app_number] => 15/493442 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 36 [patent_no_of_words] => 26716 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493442 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493442
Control flow mechanism for execution of graphics processor instructions using active channel packing Apr 20, 2017 Issued
Array ( [id] => 16737613 [patent_doc_number] => 10963265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Apparatus and method to switch configurable logic units [patent_app_type] => utility [patent_app_number] => 15/493551 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6492 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493551
Apparatus and method to switch configurable logic units Apr 20, 2017 Issued
Array ( [id] => 16446804 [patent_doc_number] => 10838733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Register context restoration based on rename register recovery [patent_app_type] => utility [patent_app_number] => 15/490013 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 65 [patent_no_of_words] => 30576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490013 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490013
Register context restoration based on rename register recovery Apr 17, 2017 Issued
Array ( [id] => 11938554 [patent_doc_number] => 20170242704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'APPARATUS AND METHOD OF IMPROVED EXTRACT INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/452631 [patent_app_country] => US [patent_app_date] => 2017-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 23225 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452631 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452631
APPARATUS AND METHOD OF IMPROVED EXTRACT INSTRUCTIONS Mar 6, 2017 Abandoned
Array ( [id] => 11629521 [patent_doc_number] => 20170139711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'CONDITIONAL INSTRUCTION END OPERATION' [patent_app_type] => utility [patent_app_number] => 15/419467 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 28941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419467 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419467
Conditional instruction end operation Jan 29, 2017 Issued
Array ( [id] => 15982125 [patent_doc_number] => 10671390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Conditional instruction end operation [patent_app_type] => utility [patent_app_number] => 15/406147 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 28209 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15406147 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/406147
Conditional instruction end operation Jan 12, 2017 Issued
Array ( [id] => 11544066 [patent_doc_number] => 20170097891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions' [patent_app_type] => utility [patent_app_number] => 15/382462 [patent_app_country] => US [patent_app_date] => 2016-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10179 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15382462 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/382462
System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions Dec 15, 2016 Abandoned
Array ( [id] => 11544001 [patent_doc_number] => 20170097826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions' [patent_app_type] => utility [patent_app_number] => 15/382476 [patent_app_country] => US [patent_app_date] => 2016-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10178 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15382476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/382476
System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions Dec 15, 2016 Abandoned
Array ( [id] => 13403533 [patent_doc_number] => 20180253309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => VECTOR DATA TRANSFER INSTRUCTION [patent_app_type] => utility [patent_app_number] => 15/759900 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15759900 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/759900
Vector data transfer instruction Sep 13, 2016 Issued
Array ( [id] => 12242099 [patent_doc_number] => 20180074962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'INDEX BASED MEMORY ACCESS' [patent_app_type] => utility [patent_app_number] => 15/261216 [patent_app_country] => US [patent_app_date] => 2016-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4986 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15261216 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/261216
Index based memory access using single instruction multiple data unit Sep 8, 2016 Issued
Array ( [id] => 11473798 [patent_doc_number] => 20170060581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'SYSTEM AND METHOD OF ACCELERATING ARBITRATION BY APPROXIMATING RELATIVE AGES' [patent_app_type] => utility [patent_app_number] => 15/241765 [patent_app_country] => US [patent_app_date] => 2016-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10601 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15241765 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/241765
System and method of accelerating arbitration by approximating relative ages Aug 18, 2016 Issued
Array ( [id] => 14457533 [patent_doc_number] => 10324727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Memory dependence prediction [patent_app_type] => utility [patent_app_number] => 15/238778 [patent_app_country] => US [patent_app_date] => 2016-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5437 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15238778 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/238778
Memory dependence prediction Aug 16, 2016 Issued
Array ( [id] => 12187522 [patent_doc_number] => 20180046459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'DATA PROCESSING' [patent_app_type] => utility [patent_app_number] => 15/236728 [patent_app_country] => US [patent_app_date] => 2016-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9179 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236728 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236728
Data processing apparatus and method for generating a status flag using predicate indicators Aug 14, 2016 Issued
Array ( [id] => 11314111 [patent_doc_number] => 20160350221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions' [patent_app_type] => utility [patent_app_number] => 15/232551 [patent_app_country] => US [patent_app_date] => 2016-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10122 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/232551
System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions Aug 8, 2016 Abandoned
Array ( [id] => 13003841 [patent_doc_number] => 10025589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Conditional transaction end instruction [patent_app_type] => utility [patent_app_number] => 15/228067 [patent_app_country] => US [patent_app_date] => 2016-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 27994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15228067 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/228067
Conditional transaction end instruction Aug 3, 2016 Issued
Array ( [id] => 11131257 [patent_doc_number] => 20160328231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS' [patent_app_type] => utility [patent_app_number] => 15/211134 [patent_app_country] => US [patent_app_date] => 2016-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 33869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15211134 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/211134
MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS Jul 14, 2016 Abandoned
Array ( [id] => 12735745 [patent_doc_number] => 20180137082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => SINGLE-CHIP MULTI-PROCESSOR COMMUNICATION [patent_app_type] => utility [patent_app_number] => 15/576680 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15576680 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/576680
Single-chip multi-processor communication May 23, 2016 Issued
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