Search

Joseph S. Herrmann

Examiner (ID: 821, Phone: (571)270-3291 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
572
Issued Applications
336
Pending Applications
66
Abandoned Applications
183

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19152981 [patent_doc_number] => 11977893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Folded instruction fetch pipeline [patent_app_type] => utility [patent_app_number] => 17/835352 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 10739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/835352
Folded instruction fetch pipeline Jun 7, 2022 Issued
Array ( [id] => 19152981 [patent_doc_number] => 11977893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Folded instruction fetch pipeline [patent_app_type] => utility [patent_app_number] => 17/835352 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 10739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/835352
Folded instruction fetch pipeline Jun 7, 2022 Issued
Array ( [id] => 19925160 [patent_doc_number] => 12299445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Register based SIMD lookup table operations [patent_app_type] => utility [patent_app_number] => 17/833504 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833504
Register based SIMD lookup table operations Jun 5, 2022 Issued
Array ( [id] => 18819509 [patent_doc_number] => 20230393849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => METHOD AND APPARATUS TO EXPEDITE SYSTEM SERVICES USING PROCESSING-IN-MEMORY (PIM) [patent_app_type] => utility [patent_app_number] => 17/804949 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804949 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804949
Method and apparatus to expedite system services using processing-in-memory (PIM) May 31, 2022 Issued
Array ( [id] => 18209907 [patent_doc_number] => 20230056168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => COMPUTER-READABLE RECORDING MEDIUM STORING COMMAND CONVERSION PROGRAM, COMMAND CONVERSION METHOD, AND COMMAND CONVERSION APPARATUS [patent_app_type] => utility [patent_app_number] => 17/828075 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828075
Computer-readable recording medium storing program for converting first single instruction multiple data (SIMD) command using first mask register into second SIMD command using second mask register, command conversion method for converting first SIMD command using first mask register into second SIMD command using second mask register, and command conversion apparatus for converting first SIMD command using first mask register into second SIMD command using second mask register May 30, 2022 Issued
Array ( [id] => 17853774 [patent_doc_number] => 20220283816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => REUSING FETCHED, FLUSHED INSTRUCTIONS AFTER AN INSTRUCTION PIPELINE FLUSH IN RESPONSE TO A HAZARD IN A PROCESSOR TO REDUCE INSTRUCTION RE-FETCHING [patent_app_type] => utility [patent_app_number] => 17/827291 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827291
Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching May 26, 2022 Issued
Array ( [id] => 18345250 [patent_doc_number] => 20230133360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => Compute-In-Memory-Based Floating-Point Processor [patent_app_type] => utility [patent_app_number] => 17/825036 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825036 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825036
Compute-In-Memory-Based Floating-Point Processor May 25, 2022 Pending
Array ( [id] => 18873554 [patent_doc_number] => 11861368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Re-enabling use of prediction table after execution state switch [patent_app_type] => utility [patent_app_number] => 17/752060 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 16780 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752060 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752060
Re-enabling use of prediction table after execution state switch May 23, 2022 Issued
Array ( [id] => 18741699 [patent_doc_number] => 20230350680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => MICROPROCESSOR WITH BASELINE AND EXTENDED REGISTER SETS [patent_app_type] => utility [patent_app_number] => 17/733728 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733728
Microprocessor with shared read and write buses and instruction issuance to multiple register sets in accordance with a time counter Apr 28, 2022 Issued
Array ( [id] => 18856181 [patent_doc_number] => 11853765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Processor authentication method [patent_app_type] => utility [patent_app_number] => 17/721193 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721193 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721193
Processor authentication method Apr 13, 2022 Issued
Array ( [id] => 18719963 [patent_doc_number] => 11797308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Fetch stage handling of indirect jumps in a processor pipeline [patent_app_type] => utility [patent_app_number] => 17/718258 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718258 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718258
Fetch stage handling of indirect jumps in a processor pipeline Apr 10, 2022 Issued
Array ( [id] => 17751456 [patent_doc_number] => 20220229661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => METHOD AND APPARATUS FOR PERFORMING REDUCTION OPERATIONS ON A PLURALITY OF ASSOCIATED DATA ELEMENT VALUES [patent_app_type] => utility [patent_app_number] => 17/712966 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712966 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712966
METHOD AND APPARATUS FOR PERFORMING REDUCTION OPERATIONS ON A PLURALITY OF ASSOCIATED DATA ELEMENT VALUES Apr 3, 2022 Abandoned
Array ( [id] => 17736618 [patent_doc_number] => 20220222077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => TAG CHECKING PROCEDURE CALLS [patent_app_type] => utility [patent_app_number] => 17/709824 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709824 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/709824
Tag checking procedure calls Mar 30, 2022 Issued
Array ( [id] => 18694775 [patent_doc_number] => 20230325192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => TRACKER FOR INDIVIDUAL BRANCH MISPREDICTION COST [patent_app_type] => utility [patent_app_number] => 17/705946 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705946 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705946
Tracker for individual branch misprediction cost Mar 27, 2022 Issued
Array ( [id] => 17722162 [patent_doc_number] => 20220214884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => ISSUING INSTRUCTIONS BASED ON RESOURCE CONFLICT CONSTRAINTS IN MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 17/703773 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703773 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703773
Issuing instructions based on resource conflict constraints in microprocessor Mar 23, 2022 Issued
Array ( [id] => 19015234 [patent_doc_number] => 11922168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Stack traces using shadow stack [patent_app_type] => utility [patent_app_number] => 17/702714 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702714 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/702714
Stack traces using shadow stack Mar 22, 2022 Issued
Array ( [id] => 17690400 [patent_doc_number] => 20220197693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => METHOD FOR PATCHING CHIP AND CHIP [patent_app_type] => utility [patent_app_number] => 17/689368 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689368 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/689368
METHOD FOR PATCHING CHIP AND CHIP Mar 7, 2022 Abandoned
Array ( [id] => 18599011 [patent_doc_number] => 20230273811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => REDUCING SILENT DATA ERRORS USING A HARDWARE MICRO-LOCKSTEP TECHNIQUE [patent_app_type] => utility [patent_app_number] => 17/682091 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682091 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682091
REDUCING SILENT DATA ERRORS USING A HARDWARE MICRO-LOCKSTEP TECHNIQUE Feb 27, 2022 Abandoned
Array ( [id] => 18539386 [patent_doc_number] => 20230244494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => Conditional Instructions Prediction [patent_app_type] => utility [patent_app_number] => 17/590719 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590719 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/590719
Conditional instructions prediction Jan 31, 2022 Issued
Array ( [id] => 17581117 [patent_doc_number] => 20220137972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => PROCESSING DEVICE WITH A MICROBRANCH TARGET BUFFER FOR BRANCH PREDICTION USING LOOP ITERATION COUNT [patent_app_type] => utility [patent_app_number] => 17/578516 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578516
Processing device with a microbranch target buffer for branch prediction using loop iteration count Jan 18, 2022 Issued
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