Search

Joseph S. Herrmann

Examiner (ID: 821, Phone: (571)270-3291 , Office: P/3746 )

Most Active Art Unit
3746
Art Unit(s)
3746
Total Applications
572
Issued Applications
336
Pending Applications
66
Abandoned Applications
183

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17899221 [patent_doc_number] => 20220308883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => METHOD AND APPARATUS FOR SCHEDULING OUT-OF-ORDER EXECUTION QUEUE IN OUT-OF-ORDER PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/611670 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17611670 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/611670
Method and apparatus for scheduling out-of-order execution queue in out-of-order processor May 20, 2021 Issued
Array ( [id] => 17260915 [patent_doc_number] => 20210373900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Exception Handling [patent_app_type] => utility [patent_app_number] => 17/322598 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322598
Exception handling May 16, 2021 Issued
Array ( [id] => 17940368 [patent_doc_number] => 11474821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-18 [patent_title] => Processor dependency-aware instruction execution [patent_app_type] => utility [patent_app_number] => 17/318252 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5886 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318252
Processor dependency-aware instruction execution May 11, 2021 Issued
Array ( [id] => 19152982 [patent_doc_number] => 11977894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Method and system for distributing instructions in reconfigurable processor and storage medium [patent_app_type] => utility [patent_app_number] => 17/770553 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6776 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17770553 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/770553
Method and system for distributing instructions in reconfigurable processor and storage medium May 6, 2021 Issued
Array ( [id] => 17962085 [patent_doc_number] => 20220342666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => ACCELERATION OF OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/240820 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 77816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240820
ACCELERATION OF OPERATIONS Apr 25, 2021 Pending
Array ( [id] => 19251043 [patent_doc_number] => 20240202033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => ACCELERATOR CONTROL SYSTEM, ACCELERATOR CONTROL METHOD AND ACCELERATOR CONTROL PROGRAM [patent_app_type] => utility [patent_app_number] => 18/287192 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18287192 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/287192
Accelerator control system using control data to perform arithmetic processing on a plurality of accelerators Apr 21, 2021 Issued
Array ( [id] => 17947985 [patent_doc_number] => 20220335004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => UNIVERSAL SYNCHRONOUS FIFO IP CORE FOR FIELD PROGRAMMABLE GATE ARRAYS [patent_app_type] => utility [patent_app_number] => 17/232634 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232634 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232634
Universal synchronous FIFO IP core for field programmable gate arrays Apr 15, 2021 Issued
Array ( [id] => 19942593 [patent_doc_number] => 12314725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Systems and methods for reducing power consumption in embedded machine learning accelerators [patent_app_type] => utility [patent_app_number] => 17/232386 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232386
Systems and methods for reducing power consumption in embedded machine learning accelerators Apr 15, 2021 Issued
Array ( [id] => 17899227 [patent_doc_number] => 20220308889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => Reconfigurable Multi-Thread Processor for Simultaneous Operations on Split Instructions and Operands [patent_app_type] => utility [patent_app_number] => 17/214804 [patent_app_country] => US [patent_app_date] => 2021-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214804 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214804
Reconfigurable multi-thread processor for simultaneous operations on split instructions and operands Mar 26, 2021 Issued
Array ( [id] => 18677840 [patent_doc_number] => 20230315487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => A SYSTEM AND METHOD FOR ENABLING RECONFIGURABLE AND FLEXIBLE MODULAR COMPUTE [patent_app_type] => utility [patent_app_number] => 17/916146 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17916146 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/916146
System and method for enabling reconfigurable and flexible modular compute Mar 25, 2021 Issued
Array ( [id] => 17098835 [patent_doc_number] => 20210286626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => CONTROL FLOW MECHANISM FOR EXECUTION OF GRAPHICS PROCESSOR INSTRUCTIONS USING ACTIVE CHANNEL PACKING [patent_app_type] => utility [patent_app_number] => 17/213453 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213453
Control flow mechanism for execution of graphics processor instructions using active channel packing Mar 25, 2021 Issued
Array ( [id] => 18104186 [patent_doc_number] => 11544072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Memory-network processor with programmable optimizations [patent_app_type] => utility [patent_app_number] => 17/203205 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 35 [patent_no_of_words] => 34219 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17203205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/203205
Memory-network processor with programmable optimizations Mar 15, 2021 Issued
Array ( [id] => 18015233 [patent_doc_number] => 11507531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Apparatus and method to switch configurable logic units [patent_app_type] => utility [patent_app_number] => 17/184945 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6542 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184945
Apparatus and method to switch configurable logic units Feb 24, 2021 Issued
Array ( [id] => 18547014 [patent_doc_number] => 11720366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Arithmetic processing apparatus using either simple or complex instruction decoder [patent_app_type] => utility [patent_app_number] => 17/182328 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3622 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182328 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182328
Arithmetic processing apparatus using either simple or complex instruction decoder Feb 22, 2021 Issued
Array ( [id] => 16856846 [patent_doc_number] => 20210157591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => STREAMING ENGINE WITH EARLY EXIT FROM LOOP LEVELS SUPPORTING EARLY EXIT LOOPS AND IRREGULAR LOOPS [patent_app_type] => utility [patent_app_number] => 17/163639 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17163639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/163639
Streaming engine with early exit from loop levels supporting early exit loops and irregular loops Jan 31, 2021 Issued
Array ( [id] => 17706793 [patent_doc_number] => 20220206799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => Apparatus for Processor with Hardware Fence and Associated Methods [patent_app_type] => utility [patent_app_number] => 17/138841 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138841 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138841
Apparatus for processor with hardware fence and associated methods Dec 29, 2020 Issued
Array ( [id] => 19899495 [patent_doc_number] => 12277419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Apparatuses, methods, and systems for instructions to convert 16-bit floating-point formats [patent_app_type] => utility [patent_app_number] => 17/134046 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 13412 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134046
Apparatuses, methods, and systems for instructions to convert 16-bit floating-point formats Dec 23, 2020 Issued
Array ( [id] => 20374070 [patent_doc_number] => 12481504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Apparatus and method for secure instruction set execution, emulation, monitoring, and prevention [patent_app_type] => utility [patent_app_number] => 17/131289 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 4523 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131289
Apparatus and method for secure instruction set execution, emulation, monitoring, and prevention Dec 21, 2020 Issued
Array ( [id] => 17690367 [patent_doc_number] => 20220197660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => CONTEXT-BASED LOOP BRANCH PREDICTION [patent_app_type] => utility [patent_app_number] => 17/128816 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128816 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128816
Context-based loop branch prediction Dec 20, 2020 Issued
Array ( [id] => 17892301 [patent_doc_number] => 11455272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Energy efficient microprocessor with index selected hardware architecture [patent_app_type] => utility [patent_app_number] => 17/117520 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9662 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117520
Energy efficient microprocessor with index selected hardware architecture Dec 9, 2020 Issued
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