
Joseph S. Herrmann
Examiner (ID: 821, Phone: (571)270-3291 , Office: P/3746 )
| Most Active Art Unit | 3746 |
| Art Unit(s) | 3746 |
| Total Applications | 572 |
| Issued Applications | 336 |
| Pending Applications | 66 |
| Abandoned Applications | 183 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16964815
[patent_doc_number] => 20210216314
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-15
[patent_title] => Performing Rounding Operations Responsive To An Instruction
[patent_app_type] => utility
[patent_app_number] => 17/108083
[patent_app_country] => US
[patent_app_date] => 2020-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5128
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108083
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/108083 | Performing Rounding Operations Responsive To An Instruction | Nov 30, 2020 | Abandoned |
Array
(
[id] => 17565129
[patent_doc_number] => 20220129278
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => DUAL BRANCH FORMAT
[patent_app_type] => utility
[patent_app_number] => 17/078296
[patent_app_country] => US
[patent_app_date] => 2020-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9017
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078296
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/078296 | Dual branch format | Oct 22, 2020 | Issued |
Array
(
[id] => 17550235
[patent_doc_number] => 20220121577
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => ASYNCHRONOUS PIPELINE MERGING USING LONG VECTOR ARBITRATION
[patent_app_type] => utility
[patent_app_number] => 17/074991
[patent_app_country] => US
[patent_app_date] => 2020-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12981
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074991
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/074991 | Asynchronous pipeline merging using long vector arbitration | Oct 19, 2020 | Issued |
Array
(
[id] => 19212782
[patent_doc_number] => 12001845
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-04
[patent_title] => Decoupled access-execute processing
[patent_app_type] => utility
[patent_app_number] => 17/755130
[patent_app_country] => US
[patent_app_date] => 2020-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 37
[patent_no_of_words] => 20482
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 390
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17755130
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/755130 | Decoupled access-execute processing | Oct 14, 2020 | Issued |
Array
(
[id] => 19956705
[patent_doc_number] => 12327120
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-10
[patent_title] => Verified stack trace generation and accelerated stack-based analysis with shadow stacks
[patent_app_type] => utility
[patent_app_number] => 17/037605
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5921
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037605
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/037605 | Verified stack trace generation and accelerated stack-based analysis with shadow stacks | Sep 28, 2020 | Issued |
Array
(
[id] => 17507563
[patent_doc_number] => 20220100666
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-31
[patent_title] => DATA PROCESSING APPARATUS AND METHOD FOR PROVIDING CANDIDATE PREDICTION ENTRIES
[patent_app_type] => utility
[patent_app_number] => 17/036442
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10654
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036442
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/036442 | Data processing apparatus and method for providing candidate prediction entries | Sep 28, 2020 | Issued |
Array
(
[id] => 18030614
[patent_doc_number] => 11513802
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-29
[patent_title] => Compressing micro-operations in scheduler entries in a processor
[patent_app_type] => utility
[patent_app_number] => 17/033883
[patent_app_country] => US
[patent_app_date] => 2020-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 12811
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033883
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/033883 | Compressing micro-operations in scheduler entries in a processor | Sep 26, 2020 | Issued |
Array
(
[id] => 19963796
[patent_doc_number] => 12333305
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-17
[patent_title] => Delayed cache writeback instructions for improved data sharing in manycore processors
[patent_app_type] => utility
[patent_app_number] => 17/033770
[patent_app_country] => US
[patent_app_date] => 2020-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 7124
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033770
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/033770 | Delayed cache writeback instructions for improved data sharing in manycore processors | Sep 25, 2020 | Issued |
Array
(
[id] => 16722174
[patent_doc_number] => 20210089321
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => INSTRUCTION PROCESSING APPARATUS, PROCESSOR, AND PROCESSING METHOD FOR INSTRUCTION ORDERING
[patent_app_type] => utility
[patent_app_number] => 17/024032
[patent_app_country] => US
[patent_app_date] => 2020-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9995
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17024032
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/024032 | Storing multiple instructions in a single reordering buffer entry | Sep 16, 2020 | Issued |
Array
(
[id] => 17744319
[patent_doc_number] => 11392386
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-19
[patent_title] => Program counter (PC)-relative load and store addressing for fused instructions
[patent_app_type] => utility
[patent_app_number] => 16/993452
[patent_app_country] => US
[patent_app_date] => 2020-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8532
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16993452
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/993452 | Program counter (PC)-relative load and store addressing for fused instructions | Aug 13, 2020 | Issued |
Array
(
[id] => 17076670
[patent_doc_number] => 11113068
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-09-07
[patent_title] => Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)
[patent_app_type] => utility
[patent_app_number] => 16/986650
[patent_app_country] => US
[patent_app_date] => 2020-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8487
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16986650
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/986650 | Performing flush recovery using parallel walks of sliced reorder buffers (SROBs) | Aug 5, 2020 | Issued |
Array
(
[id] => 17715250
[patent_doc_number] => 11379241
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-05
[patent_title] => Handling oversize store to load forwarding in a processor
[patent_app_type] => utility
[patent_app_number] => 16/943408
[patent_app_country] => US
[patent_app_date] => 2020-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 13095
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943408
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/943408 | Handling oversize store to load forwarding in a processor | Jul 29, 2020 | Issued |
Array
(
[id] => 17667077
[patent_doc_number] => 11360773
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-14
[patent_title] => Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching
[patent_app_type] => utility
[patent_app_number] => 16/907988
[patent_app_country] => US
[patent_app_date] => 2020-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 11686
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16907988
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/907988 | Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching | Jun 21, 2020 | Issued |
Array
(
[id] => 16486159
[patent_doc_number] => 20200379764
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-03
[patent_title] => PROCESSING DEVICE WITH A MICRO-BRANCH TARGET BUFFER FOR BRANCH PREDICTION
[patent_app_type] => utility
[patent_app_number] => 16/888783
[patent_app_country] => US
[patent_app_date] => 2020-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8313
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888783
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/888783 | Processing device with a microbranch target buffer for branch prediction using loop iteration count | May 30, 2020 | Issued |
Array
(
[id] => 16423744
[patent_doc_number] => 20200348942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-05
[patent_title] => Data Bus With Multi-Input Pipeline
[patent_app_type] => utility
[patent_app_number] => 16/881205
[patent_app_country] => US
[patent_app_date] => 2020-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9087
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881205
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/881205 | Data bus with multi-input pipeline | May 21, 2020 | Issued |
Array
(
[id] => 17230671
[patent_doc_number] => 20210357228
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => DETERMINING PREFETCH PATTERNS
[patent_app_type] => utility
[patent_app_number] => 15/930907
[patent_app_country] => US
[patent_app_date] => 2020-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8001
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930907
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/930907 | Determining prefetch patterns with discontinuous strides | May 12, 2020 | Issued |
Array
(
[id] => 17528563
[patent_doc_number] => 11301251
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-12
[patent_title] => Fetch stage handling of indirect jumps in a processor pipeline
[patent_app_type] => utility
[patent_app_number] => 16/856462
[patent_app_country] => US
[patent_app_date] => 2020-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8455
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856462
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/856462 | Fetch stage handling of indirect jumps in a processor pipeline | Apr 22, 2020 | Issued |
Array
(
[id] => 16346156
[patent_doc_number] => 20200310807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => Method for Forming Constant Extensions in the Same Execute Packet in a VLIW Processor
[patent_app_type] => utility
[patent_app_number] => 16/846686
[patent_app_country] => US
[patent_app_date] => 2020-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12348
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846686
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/846686 | Method for forming constant extensions in the same execute packet in a VLIW processor | Apr 12, 2020 | Issued |
Array
(
[id] => 16346154
[patent_doc_number] => 20200310805
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => PROCESSOR AUTHENTICATION METHOD
[patent_app_type] => utility
[patent_app_number] => 16/833012
[patent_app_country] => US
[patent_app_date] => 2020-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4620
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833012
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/833012 | Processor authentication method through signed instruction | Mar 26, 2020 | Issued |
Array
(
[id] => 16017683
[patent_doc_number] => 20200183685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-11
[patent_title] => PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 16/793422
[patent_app_country] => US
[patent_app_date] => 2020-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 28762
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793422
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/793422 | Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture | Feb 17, 2020 | Issued |