Search

Josetta I. Jones

Examiner (ID: 6880)

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
256
Issued Applications
249
Pending Applications
6
Abandoned Applications
1

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4237628 [patent_doc_number] => 06080596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method for forming vertical interconnect process for silicon segments with dielectric isolation' [patent_app_type] => 1 [patent_app_number] => 8/920273 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 7945 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080596.pdf [firstpage_image] =>[orig_patent_app_number] => 920273 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920273
Method for forming vertical interconnect process for silicon segments with dielectric isolation Aug 21, 1997 Issued
Array ( [id] => 3785874 [patent_doc_number] => 05840598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'LOC semiconductor assembled with room temperature adhesive' [patent_app_type] => 1 [patent_app_number] => 8/916977 [patent_app_country] => US [patent_app_date] => 1997-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2885 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/840/05840598.pdf [firstpage_image] =>[orig_patent_app_number] => 916977 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/916977
LOC semiconductor assembled with room temperature adhesive Aug 13, 1997 Issued
Array ( [id] => 4358437 [patent_doc_number] => 06168969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Surface mount IC using silicon vias in an area array format or same size as die array' [patent_app_type] => 1 [patent_app_number] => 8/909785 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3835 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/168/06168969.pdf [firstpage_image] =>[orig_patent_app_number] => 909785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/909785
Surface mount IC using silicon vias in an area array format or same size as die array Aug 11, 1997 Issued
Array ( [id] => 4030598 [patent_doc_number] => 05963782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Semiconductor component and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 8/904989 [patent_app_country] => US [patent_app_date] => 1997-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1433 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963782.pdf [firstpage_image] =>[orig_patent_app_number] => 904989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904989
Semiconductor component and method of manufacture Jul 31, 1997 Issued
Array ( [id] => 4153499 [patent_doc_number] => 06107172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Controlled linewidth reduction during gate pattern formation using an SiON BARC' [patent_app_type] => 1 [patent_app_number] => 8/905104 [patent_app_country] => US [patent_app_date] => 1997-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2476 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107172.pdf [firstpage_image] =>[orig_patent_app_number] => 905104 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905104
Controlled linewidth reduction during gate pattern formation using an SiON BARC Jul 31, 1997 Issued
Array ( [id] => 4181433 [patent_doc_number] => 06020247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Method for thin film deposition on single-crystal semiconductor substrates' [patent_app_type] => 1 [patent_app_number] => 8/904009 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3239 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020247.pdf [firstpage_image] =>[orig_patent_app_number] => 904009 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904009
Method for thin film deposition on single-crystal semiconductor substrates Jul 30, 1997 Issued
Array ( [id] => 4130707 [patent_doc_number] => 06034000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Multiple loadlock system' [patent_app_type] => 1 [patent_app_number] => 8/901485 [patent_app_country] => US [patent_app_date] => 1997-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 10 [patent_no_of_words] => 6173 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034000.pdf [firstpage_image] =>[orig_patent_app_number] => 901485 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901485
Multiple loadlock system Jul 27, 1997 Issued
Array ( [id] => 4038689 [patent_doc_number] => 05926694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Semiconductor device and a manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 8/891493 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 56 [patent_no_of_words] => 10558 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926694.pdf [firstpage_image] =>[orig_patent_app_number] => 891493 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/891493
Semiconductor device and a manufacturing method thereof Jul 10, 1997 Issued
Array ( [id] => 4237880 [patent_doc_number] => 06080614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method of making a MOS-gated semiconductor device with a single diffusion' [patent_app_type] => 1 [patent_app_number] => 8/885877 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 38 [patent_no_of_words] => 2279 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080614.pdf [firstpage_image] =>[orig_patent_app_number] => 885877 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885877
Method of making a MOS-gated semiconductor device with a single diffusion Jun 29, 1997 Issued
Array ( [id] => 3936944 [patent_doc_number] => 05981312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method for injection molded flip chip encapsulation' [patent_app_type] => 1 [patent_app_number] => 8/884232 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3705 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981312.pdf [firstpage_image] =>[orig_patent_app_number] => 884232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884232
Method for injection molded flip chip encapsulation Jun 26, 1997 Issued
Array ( [id] => 4141431 [patent_doc_number] => 06030856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Bondable compliant pads for packaging of a semiconductor chip and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/872379 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 7295 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030856.pdf [firstpage_image] =>[orig_patent_app_number] => 872379 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872379
Bondable compliant pads for packaging of a semiconductor chip and method therefor Jun 9, 1997 Issued
Array ( [id] => 4142022 [patent_doc_number] => 06030892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method of preventing overpolishing in a chemical-mechanical polishing operation' [patent_app_type] => 1 [patent_app_number] => 8/866131 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030892.pdf [firstpage_image] =>[orig_patent_app_number] => 866131 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866131
Method of preventing overpolishing in a chemical-mechanical polishing operation May 29, 1997 Issued
Array ( [id] => 4139672 [patent_doc_number] => 06060390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method of forming wiring layer' [patent_app_type] => 1 [patent_app_number] => 8/852097 [patent_app_country] => US [patent_app_date] => 1997-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5381 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060390.pdf [firstpage_image] =>[orig_patent_app_number] => 852097 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/852097
Method of forming wiring layer May 5, 1997 Issued
Array ( [id] => 3916790 [patent_doc_number] => 05951721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Process for producing solid electrolytic capacitor' [patent_app_type] => 1 [patent_app_number] => 8/839259 [patent_app_country] => US [patent_app_date] => 1997-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3762 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951721.pdf [firstpage_image] =>[orig_patent_app_number] => 839259 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839259
Process for producing solid electrolytic capacitor Apr 16, 1997 Issued
Array ( [id] => 3956833 [patent_doc_number] => 05930597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Reworkable polymer chip encapsulant' [patent_app_type] => 1 [patent_app_number] => 8/838111 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3143 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930597.pdf [firstpage_image] =>[orig_patent_app_number] => 838111 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838111
Reworkable polymer chip encapsulant Apr 14, 1997 Issued
Array ( [id] => 3957024 [patent_doc_number] => 05930609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Electronic device manufacture' [patent_app_type] => 1 [patent_app_number] => 8/818691 [patent_app_country] => US [patent_app_date] => 1997-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 7373 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930609.pdf [firstpage_image] =>[orig_patent_app_number] => 818691 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/818691
Electronic device manufacture Mar 18, 1997 Issued
Array ( [id] => 3896177 [patent_doc_number] => 05897333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Method for forming integrated composite semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/818813 [patent_app_country] => US [patent_app_date] => 1997-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2271 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897333.pdf [firstpage_image] =>[orig_patent_app_number] => 818813 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/818813
Method for forming integrated composite semiconductor devices Mar 13, 1997 Issued
Array ( [id] => 4069506 [patent_doc_number] => 05933715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Process for manufacturing discrete electronic devices' [patent_app_type] => 1 [patent_app_number] => 8/812293 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2272 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933715.pdf [firstpage_image] =>[orig_patent_app_number] => 812293 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/812293
Process for manufacturing discrete electronic devices Mar 6, 1997 Issued
Array ( [id] => 4033403 [patent_doc_number] => 05942448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method of making contacts on an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/803785 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1468 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/942/05942448.pdf [firstpage_image] =>[orig_patent_app_number] => 803785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/803785
Method of making contacts on an integrated circuit Feb 23, 1997 Issued
Array ( [id] => 3980385 [patent_doc_number] => 05910017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Increasing uniformity in a refill layer thickness for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/804452 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2966 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910017.pdf [firstpage_image] =>[orig_patent_app_number] => 804452 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804452
Increasing uniformity in a refill layer thickness for a semiconductor device Feb 20, 1997 Issued
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