Search

Joshua E. Rodden

Examiner (ID: 11866)

Most Active Art Unit
3649
Art Unit(s)
3637, 3631, 3649, 3642
Total Applications
1272
Issued Applications
718
Pending Applications
98
Abandoned Applications
472

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1214323 [patent_doc_number] => 06715023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'PCI bus switch architecture' [patent_app_type] => B1 [patent_app_number] => 09/668406 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 5978 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715023.pdf [firstpage_image] =>[orig_patent_app_number] => 09668406 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/668406
PCI bus switch architecture Sep 21, 2000 Issued
09/668952 METHOD AND APPARATUS PROVIDING MULTIPLE VOLTAGES AND FREQUENCIES SELECTABLE BASED ON REAL TIME CRITERIA TO CONTROL POWER CONSUMPTION Sep 21, 2000 Abandoned
Array ( [id] => 1225481 [patent_doc_number] => 06704826 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Digital signal isolation' [patent_app_type] => B1 [patent_app_number] => 09/666817 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3830 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704826.pdf [firstpage_image] =>[orig_patent_app_number] => 09666817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/666817
Digital signal isolation Sep 20, 2000 Issued
Array ( [id] => 1011338 [patent_doc_number] => 06901470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-31 [patent_title] => 'Data input/output system' [patent_app_type] => utility [patent_app_number] => 09/664542 [patent_app_country] => US [patent_app_date] => 2000-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 6461 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/901/06901470.pdf [firstpage_image] =>[orig_patent_app_number] => 09664542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/664542
Data input/output system Sep 17, 2000 Issued
Array ( [id] => 7628197 [patent_doc_number] => 06820163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Buffering data transfer between a chipset and memory modules' [patent_app_type] => B1 [patent_app_number] => 09/666489 [patent_app_country] => US [patent_app_date] => 2000-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1667 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820163.pdf [firstpage_image] =>[orig_patent_app_number] => 09666489 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/666489
Buffering data transfer between a chipset and memory modules Sep 17, 2000 Issued
09/663738 Functional pathway configuration at a system/IC interface Sep 14, 2000 Abandoned
Array ( [id] => 1236220 [patent_doc_number] => 06694399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Method and device for universal serial bus smart card traffic signaling' [patent_app_type] => B1 [patent_app_number] => 09/661748 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6356 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694399.pdf [firstpage_image] =>[orig_patent_app_number] => 09661748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/661748
Method and device for universal serial bus smart card traffic signaling Sep 13, 2000 Issued
Array ( [id] => 1284413 [patent_doc_number] => 06651126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Snapshot arbiter mechanism' [patent_app_type] => B1 [patent_app_number] => 09/660102 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4021 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651126.pdf [firstpage_image] =>[orig_patent_app_number] => 09660102 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660102
Snapshot arbiter mechanism Sep 11, 2000 Issued
Array ( [id] => 7621170 [patent_doc_number] => 06978331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-20 [patent_title] => 'Synchronization of interrupts with data packets' [patent_app_type] => utility [patent_app_number] => 10/070594 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4347 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/978/06978331.pdf [firstpage_image] =>[orig_patent_app_number] => 10070594 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/070594
Synchronization of interrupts with data packets Sep 6, 2000 Issued
Array ( [id] => 7628212 [patent_doc_number] => 06820148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Multiple removable non-volatile memory cards serially communicating with a host' [patent_app_type] => B1 [patent_app_number] => 09/641023 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 7473 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820148.pdf [firstpage_image] =>[orig_patent_app_number] => 09641023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/641023
Multiple removable non-volatile memory cards serially communicating with a host Aug 16, 2000 Issued
Array ( [id] => 1169734 [patent_doc_number] => 06766402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'computer in which an optional unit is installable' [patent_app_type] => B1 [patent_app_number] => 09/628817 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 4068 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766402.pdf [firstpage_image] =>[orig_patent_app_number] => 09628817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628817
computer in which an optional unit is installable Jul 30, 2000 Issued
Array ( [id] => 7631574 [patent_doc_number] => 06665763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Hot-plug storage drive' [patent_app_type] => B1 [patent_app_number] => 09/630246 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3942 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665763.pdf [firstpage_image] =>[orig_patent_app_number] => 09630246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/630246
Hot-plug storage drive Jul 30, 2000 Issued
Array ( [id] => 4422193 [patent_doc_number] => 06272576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method for extending the available number of configuration registers' [patent_app_type] => 1 [patent_app_number] => 9/619597 [patent_app_country] => US [patent_app_date] => 2000-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2800 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272576.pdf [firstpage_image] =>[orig_patent_app_number] => 619597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/619597
Method for extending the available number of configuration registers Jul 18, 2000 Issued
09/613421 Low power consumption semiconductor integrated circuit device and microprocessor Jul 9, 2000 Abandoned
Array ( [id] => 7630021 [patent_doc_number] => 06636918 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Mobile computing device and associated base stations' [patent_app_type] => B1 [patent_app_number] => 09/606638 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2903 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636918.pdf [firstpage_image] =>[orig_patent_app_number] => 09606638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606638
Mobile computing device and associated base stations Jun 28, 2000 Issued
Array ( [id] => 1353029 [patent_doc_number] => 06594722 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Mechanism for managing multiple out-of-order packet streams in a PCI host bridge' [patent_app_type] => B1 [patent_app_number] => 09/606306 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2910 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594722.pdf [firstpage_image] =>[orig_patent_app_number] => 09606306 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606306
Mechanism for managing multiple out-of-order packet streams in a PCI host bridge Jun 28, 2000 Issued
Array ( [id] => 1395142 [patent_doc_number] => 06567879 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Management of resets for interdependent dual small computer standard interface (SCSI) bus controller' [patent_app_type] => B1 [patent_app_number] => 09/605161 [patent_app_country] => US [patent_app_date] => 2000-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3962 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567879.pdf [firstpage_image] =>[orig_patent_app_number] => 09605161 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/605161
Management of resets for interdependent dual small computer standard interface (SCSI) bus controller Jun 26, 2000 Issued
Array ( [id] => 1325042 [patent_doc_number] => 06615304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Processing unit in which access to system memory is controlled' [patent_app_type] => B1 [patent_app_number] => 09/603880 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 42 [patent_no_of_words] => 29153 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615304.pdf [firstpage_image] =>[orig_patent_app_number] => 09603880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603880
Processing unit in which access to system memory is controlled Jun 25, 2000 Issued
Array ( [id] => 1431843 [patent_doc_number] => 06516366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Serial bus for connecting two integrated circuits with storage for input/output signals' [patent_app_type] => B1 [patent_app_number] => 09/580514 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 42 [patent_no_of_words] => 24081 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516366.pdf [firstpage_image] =>[orig_patent_app_number] => 09580514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/580514
Serial bus for connecting two integrated circuits with storage for input/output signals May 24, 2000 Issued
Array ( [id] => 431306 [patent_doc_number] => 07269680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'System enabling device communication in an expanded computing device' [patent_app_type] => utility [patent_app_number] => 09/819053 [patent_app_country] => US [patent_app_date] => 2000-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7285 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269680.pdf [firstpage_image] =>[orig_patent_app_number] => 09819053 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/819053
System enabling device communication in an expanded computing device May 19, 2000 Issued
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