Joshua E. Rodden

Array ( [id] => 716636 [patent_doc_number] => 07058750 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-06 [patent_title] => 'Scalable distributed memory and I/O multiprocessor system' [patent_app_type] => utility [patent_app_number] => 09/569100 [patent_app_country] => US [patent_app_date] => 2000-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4644 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/058/07058750.pdf [firstpage_image] =>[orig_patent_app_number] => 09569100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424954 [patent_doc_number] => 06230279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'System and method for dynamically controlling processing speed of a computer in response to user commands' [patent_app_type] => 1 [patent_app_number] => 9/563820 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6127 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230279.pdf [firstpage_image] =>[orig_patent_app_number] => 563820 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4335087 [patent_doc_number] => 06243787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Synchronization of interrupts with data pockets' [patent_app_type] => 1 [patent_app_number] => 9/559352 [patent_app_country] => US [patent_app_date] => 2000-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4264 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243787.pdf [firstpage_image] =>[orig_patent_app_number] => 559352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1567229 [patent_doc_number] => 06438633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'System for providing deterministic performance from a non-deterministic device' [patent_app_type] => B1 [patent_app_number] => 09/553304 [patent_app_country] => US [patent_app_date] => 2000-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5503 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438633.pdf [firstpage_image] =>[orig_patent_app_number] => 09553304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6636885 [patent_doc_number] => 20020016876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'SYSTEM HAVING DOUBLE DATA TRANSFER RATE AND INTEGRATED CIRCUIT THEREFOR' [patent_app_type] => new [patent_app_number] => 09/545648 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15151 [patent_no_of_claims] => 150 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20020016876.pdf [firstpage_image] =>[orig_patent_app_number] => 09545648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4365972 [patent_doc_number] => 06286067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method and system for the simplification of leaf-limited bridges' [patent_app_type] => 1 [patent_app_number] => 9/531062 [patent_app_country] => US [patent_app_date] => 2000-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5175 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286067.pdf [firstpage_image] =>[orig_patent_app_number] => 531062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1549503 [patent_doc_number] => 06374316 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method and system for circumscribing a topology to form ring structures' [patent_app_type] => B1 [patent_app_number] => 09/531280 [patent_app_country] => US [patent_app_date] => 2000-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9822 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374316.pdf [firstpage_image] =>[orig_patent_app_number] => 09531280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1361087 [patent_doc_number] => 06587909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Installation and removal of components of a computer' [patent_app_type] => B1 [patent_app_number] => 09/519138 [patent_app_country] => US [patent_app_date] => 2000-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 42 [patent_no_of_words] => 24635 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587909.pdf [firstpage_image] =>[orig_patent_app_number] => 09519138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426883 [patent_doc_number] => 06195719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Bus system for use with information processing apparatus' [patent_app_type] => 1 [patent_app_number] => 9/518696 [patent_app_country] => US [patent_app_date] => 2000-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 6962 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195719.pdf [firstpage_image] =>[orig_patent_app_number] => 518696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4280531 [patent_doc_number] => 06260097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method and apparatus for controlling a synchronous memory device' [patent_app_type] => 1 [patent_app_number] => 9/514872 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15087 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260097.pdf [firstpage_image] =>[orig_patent_app_number] => 514872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317730 [patent_doc_number] => 06182184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method of operating a memory device having a variable data input length' [patent_app_type] => 1 [patent_app_number] => 9/510213 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15085 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182184.pdf [firstpage_image] =>[orig_patent_app_number] => 510213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1386300 [patent_doc_number] => 06571343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Software-based voltage detection to reserve device power upon shutdown' [patent_app_type] => B1 [patent_app_number] => 09/505446 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7007 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571343.pdf [firstpage_image] =>[orig_patent_app_number] => 09505446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1365032 [patent_doc_number] => 06581122 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Smart card which operates with the USB protocol' [patent_app_type] => B1 [patent_app_number] => 09/453879 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4305 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581122.pdf [firstpage_image] =>[orig_patent_app_number] => 09453879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1279388 [patent_doc_number] => 06654844 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method and arrangement for connecting processor to ASIC' [patent_app_type] => B1 [patent_app_number] => 09/423134 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2674 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654844.pdf [firstpage_image] =>[orig_patent_app_number] => 09423134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1385717 [patent_doc_number] => 06571308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Bridging a host bus to an external bus using a host-bus-to-processor protocol translator' [patent_app_type] => B1 [patent_app_number] => 09/495041 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9455 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571308.pdf [firstpage_image] =>[orig_patent_app_number] => 09495041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422229 [patent_doc_number] => 06173348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Using a control line to insert a control message during a data transfer on a bus' [patent_app_type] => 1 [patent_app_number] => 9/494873 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9233 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173348.pdf [firstpage_image] =>[orig_patent_app_number] => 494873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317518 [patent_doc_number] => 06185644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Memory system including a plurality of memory devices and a transceiver device' [patent_app_type] => 1 [patent_app_number] => 9/487524 [patent_app_country] => US [patent_app_date] => 2000-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15069 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185644.pdf [firstpage_image] =>[orig_patent_app_number] => 487524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1526419 [patent_doc_number] => 06353867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Virtual component on-chip interface' [patent_app_type] => B1 [patent_app_number] => 09/484111 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6728 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353867.pdf [firstpage_image] =>[orig_patent_app_number] => 09484111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4376153 [patent_doc_number] => 06219735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement' [patent_app_type] => 1 [patent_app_number] => 9/477666 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5212 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219735.pdf [firstpage_image] =>[orig_patent_app_number] => 477666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1495254 [patent_doc_number] => 06418498 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Integrated system management memory for system management interrupt handler independent of BIOS and operating system' [patent_app_type] => B1 [patent_app_number] => 09/475726 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1947 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418498.pdf [firstpage_image] =>[orig_patent_app_number] => 09475726 [rel_patent_id] =>[rel_patent_doc_number] =>)