Joshua E. Rodden

Array ( [id] => 1401654 [patent_doc_number] => 06564328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Microprocessor with digital power throttle' [patent_app_type] => B1 [patent_app_number] => 09/471795 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5049 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564328.pdf [firstpage_image] =>[orig_patent_app_number] => 09471795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1308486 [patent_doc_number] => 06629172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Multi-chip addressing for the I2C bus' [patent_app_type] => B1 [patent_app_number] => 09/459720 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2668 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629172.pdf [firstpage_image] =>[orig_patent_app_number] => 09459720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1409089 [patent_doc_number] => 06557062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'System and method for low-noise control of radio frequency devices' [patent_app_type] => B1 [patent_app_number] => 09/456685 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7043 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557062.pdf [firstpage_image] =>[orig_patent_app_number] => 09456685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4365831 [patent_doc_number] => 06286057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method and arrangement for allowing a computer to communicate with a data storage device' [patent_app_type] => 1 [patent_app_number] => 9/458476 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 13983 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286057.pdf [firstpage_image] =>[orig_patent_app_number] => 458476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1308581 [patent_doc_number] => 06629185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Architecture, circuitry and method of transferring data into and/or out of an interdigitated memory array' [patent_app_type] => B1 [patent_app_number] => 09/455272 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2532 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629185.pdf [firstpage_image] =>[orig_patent_app_number] => 09455272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1508952 [patent_doc_number] => 06467003 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Fault tolerant data communication network' [patent_app_type] => B1 [patent_app_number] => 09/454054 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 24629 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467003.pdf [firstpage_image] =>[orig_patent_app_number] => 09454054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380920 [patent_doc_number] => 06256690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'System and method for facilitating multiple applications on a smart card' [patent_app_type] => 1 [patent_app_number] => 9/450028 [patent_app_country] => US [patent_app_date] => 1999-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6005 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256690.pdf [firstpage_image] =>[orig_patent_app_number] => 450028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1353004 [patent_doc_number] => 06594720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Data processing system having a PC card type interface with assigned addressing' [patent_app_type] => B1 [patent_app_number] => 09/438337 [patent_app_country] => US [patent_app_date] => 1999-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14462 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594720.pdf [firstpage_image] =>[orig_patent_app_number] => 09438337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1428907 [patent_doc_number] => 06513091 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Data routing using status-response signals' [patent_app_type] => B1 [patent_app_number] => 09/439586 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3423 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513091.pdf [firstpage_image] =>[orig_patent_app_number] => 09439586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1395202 [patent_doc_number] => 06567882 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'PCI function extension control device and method of PCI function extension control' [patent_app_type] => B1 [patent_app_number] => 09/438635 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7139 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567882.pdf [firstpage_image] =>[orig_patent_app_number] => 09438635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1430271 [patent_doc_number] => 06526466 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method and system for PLD swapping' [patent_app_type] => B1 [patent_app_number] => 09/438220 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2756 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526466.pdf [firstpage_image] =>[orig_patent_app_number] => 09438220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1430290 [patent_doc_number] => 06526469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Bus architecture employing varying width uni-directional command bus' [patent_app_type] => B1 [patent_app_number] => 09/439068 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 12972 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526469.pdf [firstpage_image] =>[orig_patent_app_number] => 09439068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1409226 [patent_doc_number] => 06557069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Processor-memory bus architecture for supporting multiple processors' [patent_app_type] => B1 [patent_app_number] => 09/439189 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 12481 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557069.pdf [firstpage_image] =>[orig_patent_app_number] => 09439189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1415432 [patent_doc_number] => 06549967 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'System for a PCI proxy link architecture' [patent_app_type] => B1 [patent_app_number] => 09/439046 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2549 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549967.pdf [firstpage_image] =>[orig_patent_app_number] => 09439046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1364936 [patent_doc_number] => 06581115 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Data processing system with configurable memory bus and scalability ports' [patent_app_type] => B1 [patent_app_number] => 09/436423 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6391 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581115.pdf [firstpage_image] =>[orig_patent_app_number] => 09436423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1425052 [patent_doc_number] => 06535939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations' [patent_app_type] => B1 [patent_app_number] => 09/436418 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6342 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535939.pdf [firstpage_image] =>[orig_patent_app_number] => 09436418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1430961 [patent_doc_number] => 06507880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens' [patent_app_type] => B1 [patent_app_number] => 09/435927 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8014 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507880.pdf [firstpage_image] =>[orig_patent_app_number] => 09435927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1420934 [patent_doc_number] => 06542949 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Method and apparatus for increased performance of a parked data bus in the non-parked direction' [patent_app_type] => B1 [patent_app_number] => 09/436206 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 15280 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542949.pdf [firstpage_image] =>[orig_patent_app_number] => 09436206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431864 [patent_doc_number] => 06516379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method and apparatus for transaction pacing to reduce destructive interference between successive transactions in a distributed symmetric multiprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/436204 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 18609 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516379.pdf [firstpage_image] =>[orig_patent_app_number] => 09436204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429186 [patent_doc_number] => 06529990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/436203 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 18501 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529990.pdf [firstpage_image] =>[orig_patent_app_number] => 09436203 [rel_patent_id] =>[rel_patent_doc_number] =>)