Search

J. R. Dean

Examiner (ID: 18699)

Most Active Art Unit
2647
Art Unit(s)
2617, 2647, 2645
Total Applications
860
Issued Applications
728
Pending Applications
61
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5947977 [patent_doc_number] => 20110106869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'Method of Addition with Multiple Operands, Corresponding Adder and Computer Program Product' [patent_app_type] => utility [patent_app_number] => 12/936337 [patent_app_country] => US [patent_app_date] => 2009-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12019 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20110106869.pdf [firstpage_image] =>[orig_patent_app_number] => 12936337 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/936337
Method of addition with multiple operands, corresponding adder and computer program product Apr 1, 2009 Issued
Array ( [id] => 5501182 [patent_doc_number] => 20090161870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'METHOD FOR KEYLESS PROTECTION OF DATA USING A LOCAL ARRAY OF DISKS' [patent_app_type] => utility [patent_app_number] => 12/394184 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20090161870.pdf [firstpage_image] =>[orig_patent_app_number] => 12394184 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/394184
Method for keyless protection of data using a local array of disks Feb 26, 2009 Issued
Array ( [id] => 5547911 [patent_doc_number] => 20090157788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'MODULAR SQUARING IN BINARY FIELD ARITHMETIC' [patent_app_type] => utility [patent_app_number] => 12/262595 [patent_app_country] => US [patent_app_date] => 2008-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4277 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20090157788.pdf [firstpage_image] =>[orig_patent_app_number] => 12262595 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/262595
MODULAR SQUARING IN BINARY FIELD ARITHMETIC Oct 30, 2008 Abandoned
Array ( [id] => 5396664 [patent_doc_number] => 20090316727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'Real-Time Optimization of TX FIR Filter for High-Speed Data Communication' [patent_app_type] => utility [patent_app_number] => 12/144610 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0316/20090316727.pdf [firstpage_image] =>[orig_patent_app_number] => 12144610 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144610
Real-time optimization of TX FIR filter for high-speed data communication Jun 22, 2008 Issued
Array ( [id] => 5399526 [patent_doc_number] => 20090319589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'USING FRACTIONAL EXPONENTS TO REDUCE THE COMPUTATIONAL COMPLEXITY OF NUMERICAL OPERATIONS' [patent_app_type] => utility [patent_app_number] => 12/143761 [patent_app_country] => US [patent_app_date] => 2008-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0319/20090319589.pdf [firstpage_image] =>[orig_patent_app_number] => 12143761 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143761
USING FRACTIONAL EXPONENTS TO REDUCE THE COMPUTATIONAL COMPLEXITY OF NUMERICAL OPERATIONS Jun 20, 2008 Abandoned
Array ( [id] => 6240325 [patent_doc_number] => 20100268752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'APPARATUS AND METHOD FOR ESTIMATING HIGH-INTEGRATION, HIGH-SPEED AND PIPELINED RECURSIVE LEAST SQUARES' [patent_app_type] => utility [patent_app_number] => 12/747599 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20100268752.pdf [firstpage_image] =>[orig_patent_app_number] => 12747599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/747599
APPARATUS AND METHOD FOR ESTIMATING HIGH-INTEGRATION, HIGH-SPEED AND PIPELINED RECURSIVE LEAST SQUARES May 15, 2008 Abandoned
Array ( [id] => 5405438 [patent_doc_number] => 20090240753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'METHOD, HARDWARE PRODUCT, AND COMPUTER PROGRAM PRODUCT FOR USING A DECIMAL FLOATING POINT UNIT TO EXECUTE FIXED POINT INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 12/051333 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20090240753.pdf [firstpage_image] =>[orig_patent_app_number] => 12051333 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051333
Execution of fixed point instructions using a decimal floating point unit Mar 18, 2008 Issued
Array ( [id] => 4741661 [patent_doc_number] => 20080235314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'METHOD OF GENERATING RANDOM ACCESS PREAMBLES IN WIRELESS COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/050023 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 22087 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235314.pdf [firstpage_image] =>[orig_patent_app_number] => 12050023 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/050023
Method of generating random access preambles in wireless communication system Mar 16, 2008 Issued
Array ( [id] => 9314701 [patent_doc_number] => 08655935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Processing apparatus and control method performing taylor series operation associated with executing floating point instruction' [patent_app_type] => utility [patent_app_number] => 12/047782 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9211 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12047782 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/047782
Processing apparatus and control method performing taylor series operation associated with executing floating point instruction Mar 12, 2008 Issued
Array ( [id] => 4699964 [patent_doc_number] => 20080222148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'LEXICOGRAPHICAL ORDERING OF REAL NUMBERS' [patent_app_type] => utility [patent_app_number] => 12/044995 [patent_app_country] => US [patent_app_date] => 2008-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4290 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222148.pdf [firstpage_image] =>[orig_patent_app_number] => 12044995 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/044995
LEXICOGRAPHICAL ORDERING OF REAL NUMBERS Mar 8, 2008 Abandoned
Array ( [id] => 8678415 [patent_doc_number] => 08386549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-26 [patent_title] => 'Reduced complexity adaptive multistage wiener filter' [patent_app_type] => utility [patent_app_number] => 12/042260 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7564 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 422 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12042260 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042260
Reduced complexity adaptive multistage wiener filter Mar 3, 2008 Issued
Array ( [id] => 4961507 [patent_doc_number] => 20080275932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Integer Division In A Manner That Counters A Power Analysis Attack' [patent_app_type] => utility [patent_app_number] => 12/040231 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6701 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20080275932.pdf [firstpage_image] =>[orig_patent_app_number] => 12040231 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/040231
Integer Division In A Manner That Counters A Power Analysis Attack Feb 28, 2008 Abandoned
Array ( [id] => 4730024 [patent_doc_number] => 20080208948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'METHODS AND APPARATUS FOR USING BOOLEAN DERIVATIVES TO PROCESS DATA' [patent_app_type] => utility [patent_app_number] => 12/038152 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20080208948.pdf [firstpage_image] =>[orig_patent_app_number] => 12038152 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/038152
METHODS AND APPARATUS FOR USING BOOLEAN DERIVATIVES TO PROCESS DATA Feb 26, 2008 Abandoned
Array ( [id] => 8448934 [patent_doc_number] => 08291001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Signal processing for media type identification' [patent_app_type] => utility [patent_app_number] => 12/037970 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12309 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12037970 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037970
Signal processing for media type identification Feb 26, 2008 Issued
Array ( [id] => 4730013 [patent_doc_number] => 20080208940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'RECONFIGURABLE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/035069 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5212 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20080208940.pdf [firstpage_image] =>[orig_patent_app_number] => 12035069 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/035069
RECONFIGURABLE CIRCUIT Feb 20, 2008 Abandoned
Array ( [id] => 4726041 [patent_doc_number] => 20080205582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'PROCESSING ELEMENT AND RECONFIGURABLE CIRCUIT INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/033969 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14928 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205582.pdf [firstpage_image] =>[orig_patent_app_number] => 12033969 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033969
PROCESSING ELEMENT AND RECONFIGURABLE CIRCUIT INCLUDING THE SAME Feb 19, 2008 Abandoned
Array ( [id] => 5587133 [patent_doc_number] => 20090106335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'Speed-Level Calculator And Calculating Method For Dynamic Voltage Scaling' [patent_app_type] => utility [patent_app_number] => 12/034109 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5384 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20090106335.pdf [firstpage_image] =>[orig_patent_app_number] => 12034109 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034109
Speed-level calculator and calculating method for dynamic voltage scaling Feb 19, 2008 Issued
Array ( [id] => 4878217 [patent_doc_number] => 20080151600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Logical Operation Circuit and Logical Operation Device' [patent_app_type] => utility [patent_app_number] => 12/034558 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11581 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151600.pdf [firstpage_image] =>[orig_patent_app_number] => 12034558 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034558
Logical Operation Circuit and Logical Operation Device Feb 19, 2008 Abandoned
Array ( [id] => 8692954 [patent_doc_number] => 08392490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Identifying decimal floating point addition operations that do not require alignment, normalization or rounding' [patent_app_type] => utility [patent_app_number] => 12/032858 [patent_app_country] => US [patent_app_date] => 2008-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2795 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12032858 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032858
Identifying decimal floating point addition operations that do not require alignment, normalization or rounding Feb 17, 2008 Issued
Array ( [id] => 8692953 [patent_doc_number] => 08392489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'ASCII to binary floating point conversion of decimal real numbers on a vector processor' [patent_app_type] => utility [patent_app_number] => 12/031706 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2358 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 508 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12031706 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031706
ASCII to binary floating point conversion of decimal real numbers on a vector processor Feb 14, 2008 Issued
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