Search

J. R. Dean

Examiner (ID: 18699)

Most Active Art Unit
2647
Art Unit(s)
2617, 2647, 2645
Total Applications
860
Issued Applications
728
Pending Applications
61
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4793735 [patent_doc_number] => 20080294709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Processing geometric data using spectral analysis' [patent_app_type] => utility [patent_app_number] => 11/805491 [patent_app_country] => US [patent_app_date] => 2007-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2522 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20080294709.pdf [firstpage_image] =>[orig_patent_app_number] => 11805491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/805491
Processing geometric data using spectral analysis May 22, 2007 Abandoned
Array ( [id] => 9443954 [patent_doc_number] => 08713085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-29 [patent_title] => 'Systems and methods for a signed magnitude adder in one\'s complement logic' [patent_app_type] => utility [patent_app_number] => 11/805362 [patent_app_country] => US [patent_app_date] => 2007-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4683 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11805362 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/805362
Systems and methods for a signed magnitude adder in one's complement logic May 21, 2007 Issued
Array ( [id] => 4780569 [patent_doc_number] => 20080288568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Low power Fast Hadamard transform' [patent_app_type] => utility [patent_app_number] => 11/803652 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5190 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288568.pdf [firstpage_image] =>[orig_patent_app_number] => 11803652 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/803652
Low power Fast Hadamard transform May 13, 2007 Abandoned
Array ( [id] => 8912202 [patent_doc_number] => 08484278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Digital architecture for DFT/IDFT hardware' [patent_app_type] => utility [patent_app_number] => 11/801903 [patent_app_country] => US [patent_app_date] => 2007-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11801903 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/801903
Digital architecture for DFT/IDFT hardware May 10, 2007 Issued
Array ( [id] => 4888783 [patent_doc_number] => 20080263115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Very long arithmetic logic unit for security processor' [patent_app_type] => utility [patent_app_number] => 11/785363 [patent_app_country] => US [patent_app_date] => 2007-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8307 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263115.pdf [firstpage_image] =>[orig_patent_app_number] => 11785363 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/785363
Very long arithmetic logic unit for security processor Apr 16, 2007 Abandoned
Array ( [id] => 7524842 [patent_doc_number] => 08028012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-27 [patent_title] => 'Dominos calculator' [patent_app_type] => utility [patent_app_number] => 11/786520 [patent_app_country] => US [patent_app_date] => 2007-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2434 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028012.pdf [firstpage_image] =>[orig_patent_app_number] => 11786520 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/786520
Dominos calculator Apr 10, 2007 Issued
Array ( [id] => 7767851 [patent_doc_number] => 08117251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Computation of a multiplication operation with an electronic circuit and method' [patent_app_type] => utility [patent_app_number] => 11/786767 [patent_app_country] => US [patent_app_date] => 2007-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6243 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117251.pdf [firstpage_image] =>[orig_patent_app_number] => 11786767 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/786767
Computation of a multiplication operation with an electronic circuit and method Apr 10, 2007 Issued
Array ( [id] => 8331354 [patent_doc_number] => 08239429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Output buffer receiving first and second input signals and outputting an output signal, and corresponding electronic circuit' [patent_app_type] => utility [patent_app_number] => 11/786424 [patent_app_country] => US [patent_app_date] => 2007-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7035 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11786424 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/786424
Output buffer receiving first and second input signals and outputting an output signal, and corresponding electronic circuit Apr 10, 2007 Issued
Array ( [id] => 4657943 [patent_doc_number] => 20080026805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Selection apparatus' [patent_app_type] => utility [patent_app_number] => 11/728945 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20080026805.pdf [firstpage_image] =>[orig_patent_app_number] => 11728945 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/728945
Selection apparatus Mar 26, 2007 Abandoned
Array ( [id] => 8000877 [patent_doc_number] => 08082286 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-20 [patent_title] => 'Method and system for soft-weighting a reiterative adaptive signal processor' [patent_app_type] => utility [patent_app_number] => 11/727422 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 8246 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082286.pdf [firstpage_image] =>[orig_patent_app_number] => 11727422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727422
Method and system for soft-weighting a reiterative adaptive signal processor Mar 25, 2007 Issued
Array ( [id] => 5260569 [patent_doc_number] => 20070214201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Units conversion using flexible, parseable syntax' [patent_app_type] => utility [patent_app_number] => 11/716764 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6043 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20070214201.pdf [firstpage_image] =>[orig_patent_app_number] => 11716764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/716764
Units conversion using flexible, parseable syntax Mar 11, 2007 Abandoned
Array ( [id] => 5248720 [patent_doc_number] => 20070244954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'FUSED BOOTH ENCODER MULTIPLEXER' [patent_app_type] => utility [patent_app_number] => 11/670357 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5520 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20070244954.pdf [firstpage_image] =>[orig_patent_app_number] => 11670357 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670357
Fused booth encoder multiplexer Jan 31, 2007 Issued
Array ( [id] => 9102482 [patent_doc_number] => 08566375 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-22 [patent_title] => 'Optimization using table gradient constraints' [patent_app_type] => utility [patent_app_number] => 11/647107 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 16457 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11647107 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647107
Optimization using table gradient constraints Dec 26, 2006 Issued
Array ( [id] => 9248203 [patent_doc_number] => 08612504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'IFFT processing in wireless communications' [patent_app_type] => utility [patent_app_number] => 11/612456 [patent_app_country] => US [patent_app_date] => 2006-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 11926 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 430 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11612456 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612456
IFFT processing in wireless communications Dec 17, 2006 Issued
Array ( [id] => 7537481 [patent_doc_number] => 08051123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-01 [patent_title] => 'Multipurpose functional unit with double-precision and filtering operations' [patent_app_type] => utility [patent_app_number] => 11/611800 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 22885 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 461 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051123.pdf [firstpage_image] =>[orig_patent_app_number] => 11611800 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/611800
Multipurpose functional unit with double-precision and filtering operations Dec 14, 2006 Issued
Array ( [id] => 8366364 [patent_doc_number] => 08255440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-28 [patent_title] => 'Increasing logic efficiency for exclusive OR (XOR) expressions' [patent_app_type] => utility [patent_app_number] => 11/567709 [patent_app_country] => US [patent_app_date] => 2006-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5197 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11567709 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/567709
Increasing logic efficiency for exclusive OR (XOR) expressions Dec 5, 2006 Issued
Array ( [id] => 4836094 [patent_doc_number] => 20080133636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'HIGH PASS FILTER' [patent_app_type] => utility [patent_app_number] => 11/567020 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2207 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20080133636.pdf [firstpage_image] =>[orig_patent_app_number] => 11567020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/567020
HIGH PASS FILTER Dec 4, 2006 Abandoned
Array ( [id] => 7510022 [patent_doc_number] => 08037120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'System and method for an efficient comparison operation of multi-bit vectors in a digital logic circuit' [patent_app_type] => utility [patent_app_number] => 11/566692 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5888 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037120.pdf [firstpage_image] =>[orig_patent_app_number] => 11566692 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/566692
System and method for an efficient comparison operation of multi-bit vectors in a digital logic circuit Dec 4, 2006 Issued
Array ( [id] => 5178956 [patent_doc_number] => 20070180016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'METHOD OF OPERAND WIDTH REDUCTION TO ENABLE USAGE OF NARROWER SATURATION ADDER' [patent_app_type] => utility [patent_app_number] => 11/560165 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2809 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20070180016.pdf [firstpage_image] =>[orig_patent_app_number] => 11560165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/560165
Method of operand width reduction to enable usage of narrower saturation adder Nov 14, 2006 Issued
Array ( [id] => 4646779 [patent_doc_number] => 08024391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'Modular multiplication method with precomputation using one known operand' [patent_app_type] => utility [patent_app_number] => 11/556894 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3837 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/024/08024391.pdf [firstpage_image] =>[orig_patent_app_number] => 11556894 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556894
Modular multiplication method with precomputation using one known operand Nov 5, 2006 Issued
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