Search

Juan Carlos Ochoa

Examiner (ID: 13650, Phone: (571)272-2625 , Office: P/2123 )

Most Active Art Unit
2123
Art Unit(s)
2123, 2186, 2146, 2187, 2127
Total Applications
672
Issued Applications
410
Pending Applications
75
Abandoned Applications
195

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6665062 [patent_doc_number] => 20030204389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Method for numerically simulating an electrical circuit' [patent_app_type] => new [patent_app_number] => 10/422580 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9660 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20030204389.pdf [firstpage_image] =>[orig_patent_app_number] => 10422580 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422580
Method for numerically simulating an electrical circuit Apr 23, 2003 Issued
Array ( [id] => 598000 [patent_doc_number] => 07444274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-28 [patent_title] => 'Method and system for verifying circuit designs through propagation of assertions' [patent_app_type] => utility [patent_app_number] => 10/422389 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6727 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444274.pdf [firstpage_image] =>[orig_patent_app_number] => 10422389 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422389
Method and system for verifying circuit designs through propagation of assertions Apr 22, 2003 Issued
Array ( [id] => 7299004 [patent_doc_number] => 20040215437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'System and method for improved accuracy of standard cell timing models' [patent_app_type] => new [patent_app_number] => 10/421522 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4529 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215437.pdf [firstpage_image] =>[orig_patent_app_number] => 10421522 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/421522
System and method for improved accuracy of standard cell timing models Apr 21, 2003 Abandoned
Array ( [id] => 7299005 [patent_doc_number] => 20040215438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Hardware and software co-simulation using estimated adjustable timing annotations' [patent_app_type] => new [patent_app_number] => 10/420376 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215438.pdf [firstpage_image] =>[orig_patent_app_number] => 10420376 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/420376
Hardware and software co-simulation using estimated adjustable timing annotations Apr 21, 2003 Issued
Array ( [id] => 7160718 [patent_doc_number] => 20040075436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Calculating method for inductance in a semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/421005 [patent_app_country] => US [patent_app_date] => 2003-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8068 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20040075436.pdf [firstpage_image] =>[orig_patent_app_number] => 10421005 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/421005
Calculating method for inductance in a semiconductor integrated circuit Apr 20, 2003 Abandoned
Array ( [id] => 6826031 [patent_doc_number] => 20030236653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Simulation method and system for design of aperture in exposure apparatus and recording medium in which the simulation method is recorded' [patent_app_type] => new [patent_app_number] => 10/418220 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4127 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20030236653.pdf [firstpage_image] =>[orig_patent_app_number] => 10418220 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/418220
Simulation method and system for design of aperture in exposure apparatus and recording medium in which the simulation method is recorded Apr 17, 2003 Issued
Array ( [id] => 7442466 [patent_doc_number] => 20040210685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Block modeling input/output buffer' [patent_app_type] => new [patent_app_number] => 10/417404 [patent_app_country] => US [patent_app_date] => 2003-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6841 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20040210685.pdf [firstpage_image] =>[orig_patent_app_number] => 10417404 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/417404
Block modeling input/output buffer Apr 15, 2003 Issued
Array ( [id] => 7476178 [patent_doc_number] => 20040098173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Method for operating an electrostatic filter' [patent_app_type] => new [patent_app_number] => 10/398731 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2190 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20040098173.pdf [firstpage_image] =>[orig_patent_app_number] => 10398731 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/398731
Method for operating an electrostatic filter Apr 8, 2003 Abandoned
Array ( [id] => 7672406 [patent_doc_number] => 20040181373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Visual simulation of dynamic moving bodies' [patent_app_type] => new [patent_app_number] => 10/386732 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5062 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20040181373.pdf [firstpage_image] =>[orig_patent_app_number] => 10386732 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/386732
Visual simulation of dynamic moving bodies Mar 11, 2003 Abandoned
Array ( [id] => 7172103 [patent_doc_number] => 20040078184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Logic emulator' [patent_app_type] => new [patent_app_number] => 10/385508 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16872 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078184.pdf [firstpage_image] =>[orig_patent_app_number] => 10385508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/385508
Logic emulator Mar 11, 2003 Abandoned
Array ( [id] => 6770960 [patent_doc_number] => 20030216900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Method and system for calculating the electrostatic force due to a system of charged bodies in molecular modeling' [patent_app_type] => new [patent_app_number] => 10/371978 [patent_app_country] => US [patent_app_date] => 2003-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7289 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20030216900.pdf [firstpage_image] =>[orig_patent_app_number] => 10371978 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/371978
Method and system for calculating the electrostatic force due to a system of charged bodies in molecular modeling Feb 20, 2003 Abandoned
Array ( [id] => 5200330 [patent_doc_number] => 20070299648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Reuse of learned information to simplify functional verification of a digital circuit' [patent_app_type] => utility [patent_app_number] => 10/340555 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15096 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20070299648.pdf [firstpage_image] =>[orig_patent_app_number] => 10340555 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/340555
Reuse of learned information to simplify functional verification of a digital circuit Jan 9, 2003 Abandoned
Array ( [id] => 7309615 [patent_doc_number] => 20040117747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Method for providing cycle-by-cycle ad hoc verification in a hardware-accelerated environment' [patent_app_type] => new [patent_app_number] => 10/320108 [patent_app_country] => US [patent_app_date] => 2002-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20040117747.pdf [firstpage_image] =>[orig_patent_app_number] => 10320108 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/320108
Method for providing cycle-by-cycle ad HOC verification in a hardware-accelerated environment Dec 15, 2002 Issued
Array ( [id] => 308932 [patent_doc_number] => 07533012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Multi-user web simulator' [patent_app_type] => utility [patent_app_number] => 10/319057 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13101 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/533/07533012.pdf [firstpage_image] =>[orig_patent_app_number] => 10319057 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/319057
Multi-user web simulator Dec 12, 2002 Issued
Array ( [id] => 622802 [patent_doc_number] => 07143025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Web simulator' [patent_app_type] => utility [patent_app_number] => 10/319062 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13324 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143025.pdf [firstpage_image] =>[orig_patent_app_number] => 10319062 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/319062
Web simulator Dec 12, 2002 Issued
Array ( [id] => 881418 [patent_doc_number] => 07359846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-15 [patent_title] => 'Modeling an ASIC based on static pipeline delays' [patent_app_type] => utility [patent_app_number] => 10/313597 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6077 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/359/07359846.pdf [firstpage_image] =>[orig_patent_app_number] => 10313597 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/313597
Modeling an ASIC based on static pipeline delays Dec 4, 2002 Issued
Array ( [id] => 6654129 [patent_doc_number] => 20030105618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Diagnostic method for correctly handling discontinuities during circuit simulation or mixed-signal simulation' [patent_app_type] => new [patent_app_number] => 10/310443 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5365 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 404 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20030105618.pdf [firstpage_image] =>[orig_patent_app_number] => 10310443 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/310443
Diagnostic method for correctly handling discontinuities during circuit simulation or mixed-signal simulation Dec 4, 2002 Abandoned
Array ( [id] => 7472589 [patent_doc_number] => 20040102944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'System and method for detecting accesses to non-existing hardware entities using architectural simulation' [patent_app_type] => new [patent_app_number] => 10/303427 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3086 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20040102944.pdf [firstpage_image] =>[orig_patent_app_number] => 10303427 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/303427
System and method for detecting accesses to non-existing hardware entities using architectural simulation Nov 24, 2002 Issued
Array ( [id] => 7472585 [patent_doc_number] => 20040102943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Method and apparatus for simulating a magnetoresistive random access memory (MRAM)' [patent_app_type] => new [patent_app_number] => 10/302203 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4326 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20040102943.pdf [firstpage_image] =>[orig_patent_app_number] => 10302203 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302203
Method and apparatus for simulating a magnetoresistive random access memory (MRAM) Nov 21, 2002 Issued
Array ( [id] => 279638 [patent_doc_number] => 07558722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Debug method for mismatches occurring during the simulation of scan patterns' [patent_app_type] => utility [patent_app_number] => 10/299129 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2383 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558722.pdf [firstpage_image] =>[orig_patent_app_number] => 10299129 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/299129
Debug method for mismatches occurring during the simulation of scan patterns Nov 18, 2002 Issued
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