
Julia Slutsker
Examiner (ID: 6859, Phone: (571)270-3849 , Office: P/2891 )
| Most Active Art Unit | 2891 |
| Art Unit(s) | 4193, 2891 |
| Total Applications | 1221 |
| Issued Applications | 866 |
| Pending Applications | 116 |
| Abandoned Applications | 260 |
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|---|---|---|---|
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