Search

June Y. Sison

Examiner (ID: 12192, Phone: (571)270-5693 , Office: P/2443 )

Most Active Art Unit
2443
Art Unit(s)
2455, 2443
Total Applications
528
Issued Applications
352
Pending Applications
50
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6256062 [patent_doc_number] => 20100295094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'ESD Protection Apparatus and Electrical Circuit Including Same' [patent_app_type] => utility [patent_app_number] => 12/848668 [patent_app_country] => US [patent_app_date] => 2010-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5037 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0295/20100295094.pdf [firstpage_image] =>[orig_patent_app_number] => 12848668 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/848668
ESD protection apparatus and electrical circuit including same Aug 1, 2010 Issued
Array ( [id] => 9355881 [patent_doc_number] => 08674419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Method of forming a CMOS structure having gate insulation films of different thicknesses' [patent_app_type] => utility [patent_app_number] => 12/838598 [patent_app_country] => US [patent_app_date] => 2010-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 61 [patent_no_of_words] => 19077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12838598 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/838598
Method of forming a CMOS structure having gate insulation films of different thicknesses Jul 18, 2010 Issued
Array ( [id] => 6441000 [patent_doc_number] => 20100279470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'PACKAGE WITH MULTIPLE DIES' [patent_app_type] => utility [patent_app_number] => 12/838022 [patent_app_country] => US [patent_app_date] => 2010-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3674 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20100279470.pdf [firstpage_image] =>[orig_patent_app_number] => 12838022 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/838022
Package with multiple dies Jul 15, 2010 Issued
Array ( [id] => 8560118 [patent_doc_number] => 08334181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-18 [patent_title] => 'Germanium MOSFET devices and methods for making same' [patent_app_type] => utility [patent_app_number] => 12/836378 [patent_app_country] => US [patent_app_date] => 2010-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 4870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12836378 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/836378
Germanium MOSFET devices and methods for making same Jul 13, 2010 Issued
Array ( [id] => 10888661 [patent_doc_number] => 08912657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/801933 [patent_app_country] => US [patent_app_date] => 2010-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11465 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12801933 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801933
Semiconductor device Jul 1, 2010 Issued
Array ( [id] => 8802781 [patent_doc_number] => 08441056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'NROM memory cell, memory array, related devices and methods' [patent_app_type] => utility [patent_app_number] => 12/795906 [patent_app_country] => US [patent_app_date] => 2010-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 11237 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12795906 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/795906
NROM memory cell, memory array, related devices and methods Jun 7, 2010 Issued
Array ( [id] => 8664981 [patent_doc_number] => 08378444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Photodiode and method of fabricating photodiode' [patent_app_type] => utility [patent_app_number] => 12/781850 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 7497 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12781850 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/781850
Photodiode and method of fabricating photodiode May 17, 2010 Issued
Array ( [id] => 8571594 [patent_doc_number] => 08338239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'High performance devices and high density devices on single chip' [patent_app_type] => utility [patent_app_number] => 12/781896 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2528 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12781896 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/781896
High performance devices and high density devices on single chip May 17, 2010 Issued
Array ( [id] => 7584221 [patent_doc_number] => 20110278731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'METHOD FOR INTEGRATED CIRCUIT DESIGN AND MANUFACTURE USING DIAGONAL MINIMUM-WIDTH PATTERNS' [patent_app_type] => utility [patent_app_number] => 12/779031 [patent_app_country] => US [patent_app_date] => 2010-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6450 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20110278731.pdf [firstpage_image] =>[orig_patent_app_number] => 12779031 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/779031
Method for integrated circuit design and manufacture using diagonal minimum-width patterns May 11, 2010 Issued
Array ( [id] => 8577605 [patent_doc_number] => 08343815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'TFET with nanowire source' [patent_app_type] => utility [patent_app_number] => 12/777881 [patent_app_country] => US [patent_app_date] => 2010-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1396 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12777881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/777881
TFET with nanowire source May 10, 2010 Issued
Array ( [id] => 9245181 [patent_doc_number] => 08609461 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-17 [patent_title] => 'Semiconductor epitaxy on diamond for heat spreading applications' [patent_app_type] => utility [patent_app_number] => 12/777907 [patent_app_country] => US [patent_app_date] => 2010-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12777907 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/777907
Semiconductor epitaxy on diamond for heat spreading applications May 10, 2010 Issued
Array ( [id] => 8629835 [patent_doc_number] => 08361907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Directionally etched nanowire field effect transistors' [patent_app_type] => utility [patent_app_number] => 12/776485 [patent_app_country] => US [patent_app_date] => 2010-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 2795 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12776485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/776485
Directionally etched nanowire field effect transistors May 9, 2010 Issued
Array ( [id] => 8458466 [patent_doc_number] => 08294135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'High power density photo-electronic and photo-voltaic materials and methods of making' [patent_app_type] => utility [patent_app_number] => 12/776796 [patent_app_country] => US [patent_app_date] => 2010-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2931 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12776796 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/776796
High power density photo-electronic and photo-voltaic materials and methods of making May 9, 2010 Issued
Array ( [id] => 9844170 [patent_doc_number] => 08946085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Semiconductor process and structure' [patent_app_type] => utility [patent_app_number] => 12/774823 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2238 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12774823 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774823
Semiconductor process and structure May 5, 2010 Issued
Array ( [id] => 6208123 [patent_doc_number] => 20110133148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/773228 [patent_app_country] => US [patent_app_date] => 2010-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133148.pdf [firstpage_image] =>[orig_patent_app_number] => 12773228 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/773228
Resistive memory device and method of fabricating the same May 3, 2010 Issued
Array ( [id] => 7571020 [patent_doc_number] => 20110266676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'METHOD FOR FORMING INTERCONNECTION LINE AND SEMICONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/772294 [patent_app_country] => US [patent_app_date] => 2010-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4886 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266676.pdf [firstpage_image] =>[orig_patent_app_number] => 12772294 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/772294
METHOD FOR FORMING INTERCONNECTION LINE AND SEMICONDUCTOR STRUCTURE May 2, 2010 Abandoned
Array ( [id] => 7504685 [patent_doc_number] => 08035162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'System and method for ESD protection' [patent_app_type] => utility [patent_app_number] => 12/729040 [patent_app_country] => US [patent_app_date] => 2010-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 80 [patent_no_of_words] => 42951 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/035/08035162.pdf [firstpage_image] =>[orig_patent_app_number] => 12729040 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/729040
System and method for ESD protection Mar 21, 2010 Issued
Array ( [id] => 4485500 [patent_doc_number] => 07883906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Integration of capacitive elements in the form of perovskite ceramic' [patent_app_type] => utility [patent_app_number] => 12/716289 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1841 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/883/07883906.pdf [firstpage_image] =>[orig_patent_app_number] => 12716289 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716289
Integration of capacitive elements in the form of perovskite ceramic Mar 2, 2010 Issued
Array ( [id] => 6427210 [patent_doc_number] => 20100151638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'ANISOTROPIC STRESS GENERATION BY STRESS-GENERATING LINERS HAVING A SUBLITHOGRAPHIC WIDTH' [patent_app_type] => utility [patent_app_number] => 12/712369 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8058 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20100151638.pdf [firstpage_image] =>[orig_patent_app_number] => 12712369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712369
Anisotropic stress generation by stress-generating liners having a sublithographic width Feb 24, 2010 Issued
Array ( [id] => 6036267 [patent_doc_number] => 20110089405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/992049 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 16784 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20110089405.pdf [firstpage_image] =>[orig_patent_app_number] => 12992049 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/992049
Systems and methods for fabrication of superconducting integrated circuits Feb 24, 2010 Issued
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