Search

Jung H. Hur

Examiner (ID: 3320)

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1180
Issued Applications
1001
Pending Applications
13
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19335331 [patent_doc_number] => 20240249761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => POWER SUPPLY GENERATOR ASSIST [patent_app_type] => utility [patent_app_number] => 18/626718 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626718 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626718
POWER SUPPLY GENERATOR ASSIST Apr 3, 2024 Pending
Array ( [id] => 19634349 [patent_doc_number] => 20240412798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => Method for Scanning a Memory Array [patent_app_type] => utility [patent_app_number] => 18/403700 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403700
Method for Scanning a Memory Array Jan 2, 2024 Pending
Array ( [id] => 19005998 [patent_doc_number] => 20240070069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MEMORY DEVICE INTERFACE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/215474 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18215474 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/215474
Memory device interface and method Jun 27, 2023 Issued
Array ( [id] => 19781309 [patent_doc_number] => 12230347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => System and memory with configurable metadata portion [patent_app_type] => utility [patent_app_number] => 18/322997 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 23376 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322997
System and memory with configurable metadata portion May 23, 2023 Issued
Array ( [id] => 19626837 [patent_doc_number] => 12165684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Midpoint sensing reference generation for STT-MRAM [patent_app_type] => utility [patent_app_number] => 18/297793 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18297793 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/297793
Midpoint sensing reference generation for STT-MRAM Apr 9, 2023 Issued
Array ( [id] => 19912359 [patent_doc_number] => 12288577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Sensing amplifier, method and controller for sensing memory cell [patent_app_type] => utility [patent_app_number] => 18/177749 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177749 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177749
Sensing amplifier, method and controller for sensing memory cell Mar 1, 2023 Issued
Array ( [id] => 18585735 [patent_doc_number] => 20230267999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => MEMORY DEVICE AND METHOD FOR OPERATING SAID MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/171426 [patent_app_country] => US [patent_app_date] => 2023-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171426 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171426
Memory device and method for testing the memory device that bypasses memory cells Feb 19, 2023 Issued
Array ( [id] => 18957130 [patent_doc_number] => 20240045457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => POWER SUPPLY CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/168647 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168647 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168647
Power supply circuit with power voltage networks to selectively pull up power voltage and memory including the same Feb 13, 2023 Issued
Array ( [id] => 19679123 [patent_doc_number] => 12190994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Single port memory with multiple memory operations per clock cycle [patent_app_type] => utility [patent_app_number] => 18/090574 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090574 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090574
Single port memory with multiple memory operations per clock cycle Dec 28, 2022 Issued
Array ( [id] => 19900055 [patent_doc_number] => 12277987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Error handling device, semiconductor memory device including the same, and error handling method including cross sensing operation [patent_app_type] => utility [patent_app_number] => 18/148357 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148357 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/148357
Error handling device, semiconductor memory device including the same, and error handling method including cross sensing operation Dec 28, 2022 Issued
Array ( [id] => 18881189 [patent_doc_number] => 20240004558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/077727 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077727
Semiconductor memory device and method of operating the same including detrap operation for lowering memory cell threshold voltages Dec 7, 2022 Issued
Array ( [id] => 18904537 [patent_doc_number] => 20240020022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/073130 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18073130 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/073130
Nonvolatile memory device including selective bit line and source line precharge times and operating method thereof Nov 30, 2022 Issued
Array ( [id] => 18898353 [patent_doc_number] => 20240013838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/070199 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/070199
Memory device and operating method of the memory device for controlling program operation Nov 27, 2022 Issued
Array ( [id] => 18265616 [patent_doc_number] => 20230086858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => METHOD FOR ENHANCING TUNNEL MAGNETORESISTANCE IN MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/994407 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994407 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994407
Enhancing tunnel magnetoresistance in memory device comprising a memory cell with a memory element coupled between a switch and a negative resistance device Nov 27, 2022 Issued
Array ( [id] => 18365702 [patent_doc_number] => 20230147293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => APPARATUS AND METHOD FOR ZQ CALIBRATION OF DATA TRANSMISSION DRIVING CIRCUIT IN MEMORY CHIP PACKAGE OF MULTI-MEMORY DIE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/983016 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/983016
Apparatus and method for ZQ calibration of data transmission driving circuit in memory chip package of multi-memory die structure Nov 7, 2022 Issued
Array ( [id] => 18251666 [patent_doc_number] => 20230078705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => REFERENCE VOLTAGE ADJUSTMENT BASED ON POST-DECODING AND PRE-DECODING STATE INFORMATION [patent_app_type] => utility [patent_app_number] => 17/980474 [patent_app_country] => US [patent_app_date] => 2022-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17980474 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/980474
Reference voltage adjustment based on post-decoding and pre-decoding state information Nov 2, 2022 Issued
Array ( [id] => 19856944 [patent_doc_number] => 12259778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Memory system determining a degraded word line based on fail bit count and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/051767 [patent_app_country] => US [patent_app_date] => 2022-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9580 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051767
Memory system determining a degraded word line based on fail bit count and operating method thereof Oct 31, 2022 Issued
Array ( [id] => 19054466 [patent_doc_number] => 20240096435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => BUILT-IN SELF-TEST CIRCUIT FOR ROW HAMMERING IN MEMORY [patent_app_type] => utility [patent_app_number] => 17/946085 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946085
Built-in self-test circuit for row hammering in memory Sep 15, 2022 Issued
Array ( [id] => 19900044 [patent_doc_number] => 12277976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Storage device, non-volatile memory, and method of operating program of non-volatile memory including counting a number of on-cells during verification [patent_app_type] => utility [patent_app_number] => 17/941570 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 7463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941570 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/941570
Storage device, non-volatile memory, and method of operating program of non-volatile memory including counting a number of on-cells during verification Sep 8, 2022 Issued
Array ( [id] => 18112650 [patent_doc_number] => 20230005530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => CONCURRENT MULTI-BIT ACCESS IN CROSS-POINT ARRAY [patent_app_type] => utility [patent_app_number] => 17/939826 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939826 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/939826
Concurrent multi-bit self-referenced read of programmable resistance memory cells in cross-point array Sep 6, 2022 Issued
Menu