Search

Jung H. Hur

Examiner (ID: 14455, Phone: (571)272-1870 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1178
Issued Applications
1001
Pending Applications
11
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14784373 [patent_doc_number] => 20190267084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => METHOD OF OPERATING RESISTIVE MEMORY DEVICE CAPABLE OF REDUCING WRITE LATENCY [patent_app_type] => utility [patent_app_number] => 16/116141 [patent_app_country] => US [patent_app_date] => 2018-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/116141
Method of operating resistive memory device capable of reducing write latency Aug 28, 2018 Issued
Array ( [id] => 15014689 [patent_doc_number] => 10453499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Apparatuses and methods for performing an in-place inversion using sensing circuitry [patent_app_type] => utility [patent_app_number] => 16/107724 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 24673 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107724 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107724
Apparatuses and methods for performing an in-place inversion using sensing circuitry Aug 20, 2018 Issued
Array ( [id] => 15532055 [patent_doc_number] => 20200058333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => APPARATUSES AND METHODS FOR LATCHING DATA INPUT BITS [patent_app_type] => utility [patent_app_number] => 16/103151 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103151 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103151
Apparatuses and methods for latching data input bits Aug 13, 2018 Issued
Array ( [id] => 15640805 [patent_doc_number] => 10593405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Read process in a semiconductor memory device including a memory cell transistor [patent_app_type] => utility [patent_app_number] => 16/101645 [patent_app_country] => US [patent_app_date] => 2018-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5747 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16101645 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/101645
Read process in a semiconductor memory device including a memory cell transistor Aug 12, 2018 Issued
Array ( [id] => 16593659 [patent_doc_number] => 10902935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Access schemes for access line faults in a memory device [patent_app_type] => utility [patent_app_number] => 16/102489 [patent_app_country] => US [patent_app_date] => 2018-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 36839 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102489 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/102489
Access schemes for access line faults in a memory device Aug 12, 2018 Issued
Array ( [id] => 13962787 [patent_doc_number] => 20190057738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => RESISTIVE MEMORY STORAGE APPARATUS AND WRITING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/048350 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/048350
Resistive memory storage apparatus and writing method thereof including disturbance voltage Jul 29, 2018 Issued
Array ( [id] => 15138993 [patent_doc_number] => 10482978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Read voltage optimization method, memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 16/048366 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17688 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 506 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048366 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/048366
Read voltage optimization method, memory storage device and memory control circuit unit Jul 29, 2018 Issued
Array ( [id] => 13848001 [patent_doc_number] => 20190027485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => MEMORY ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 16/040075 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16040075 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/040075
Memory arrangement and detection circuit for data protection Jul 18, 2018 Issued
Array ( [id] => 13908755 [patent_doc_number] => 20190043582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/030136 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030136 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030136
Ternary content addressable memory wiring arrangement Jul 8, 2018 Issued
Array ( [id] => 15856879 [patent_doc_number] => 10643734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => System and method for counting fail bit and reading out the same [patent_app_type] => utility [patent_app_number] => 16/020806 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7298 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16020806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/020806
System and method for counting fail bit and reading out the same Jun 26, 2018 Issued
Array ( [id] => 16218250 [patent_doc_number] => 10734070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Programming selection devices in non-volatile memory strings [patent_app_type] => utility [patent_app_number] => 16/019456 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 11793 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16019456 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/019456
Programming selection devices in non-volatile memory strings Jun 25, 2018 Issued
Array ( [id] => 15259691 [patent_doc_number] => 20190378579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => NON-VOLATILE MEMORY WITH COUNTERMEASURE FOR PROGRAM DISTURB INCLUDING DELAYED RAMP DOWN DURING PROGRAM VERIFY [patent_app_type] => utility [patent_app_number] => 16/002793 [patent_app_country] => US [patent_app_date] => 2018-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16002793 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/002793
Non-volatile memory with countermeasure for program disturb including delayed ramp down during program verify Jun 6, 2018 Issued
Array ( [id] => 15259669 [patent_doc_number] => 20190378568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => TECHNIQUES FOR PROGRAMMING MULTI-LEVEL SELF-SELECTING MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/001798 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001798 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001798
Techniques for programming multi-level self-selecting memory cell Jun 5, 2018 Issued
Array ( [id] => 16201747 [patent_doc_number] => 10726922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Memory device with connected word lines for fast programming [patent_app_type] => utility [patent_app_number] => 16/000237 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 51 [patent_no_of_words] => 24284 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000237 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/000237
Memory device with connected word lines for fast programming Jun 4, 2018 Issued
Array ( [id] => 17002699 [patent_doc_number] => 11081522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Wiring line layout in a semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/615243 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 15510 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16615243 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/615243
Wiring line layout in a semiconductor memory device Apr 16, 2018 Issued
Array ( [id] => 16324011 [patent_doc_number] => 10783981 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-22 [patent_title] => Semiconductor memory capable of reducing an initial turn-on voltage of a memory cell using a stress pulse in a test mode, and method for driving the same [patent_app_type] => utility [patent_app_number] => 15/945620 [patent_app_country] => US [patent_app_date] => 2018-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 12790 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945620 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/945620
Semiconductor memory capable of reducing an initial turn-on voltage of a memory cell using a stress pulse in a test mode, and method for driving the same Apr 3, 2018 Issued
Array ( [id] => 18130560 [patent_doc_number] => 11556771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Semiconductor neural network device including a synapse circuit comprising memory cells and an activation function circuit [patent_app_type] => utility [patent_app_number] => 16/603710 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 37 [patent_no_of_words] => 26192 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 436 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603710 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603710
Semiconductor neural network device including a synapse circuit comprising memory cells and an activation function circuit Apr 1, 2018 Issued
Array ( [id] => 16201744 [patent_doc_number] => 10726919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Apparatuses and methods for comparing data patterns in memory [patent_app_type] => utility [patent_app_number] => 15/941896 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 24867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941896 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941896
Apparatuses and methods for comparing data patterns in memory Mar 29, 2018 Issued
Array ( [id] => 14078805 [patent_doc_number] => 20190088290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => MEMORY CHIP WITH REDUCED POWER CONSUMPTION, BUFFER CHIP MODULE CONTROLLING THE SAME AND MEMORY MODULE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/926638 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15926638 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/926638
Memory chip with reduced power consumption, buffer chip module controlling the same and memory module including the same Mar 19, 2018 Issued
Array ( [id] => 15581163 [patent_doc_number] => 10580976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Three-dimensional phase change memory device having a laterally constricted element and method of making the same [patent_app_type] => utility [patent_app_number] => 15/924944 [patent_app_country] => US [patent_app_date] => 2018-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 82 [patent_no_of_words] => 15268 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15924944 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/924944
Three-dimensional phase change memory device having a laterally constricted element and method of making the same Mar 18, 2018 Issued
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