Search

Jung H. Hur

Examiner (ID: 14455, Phone: (571)272-1870 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1178
Issued Applications
1001
Pending Applications
11
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14542519 [patent_doc_number] => 20190206881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => Memory Cell With A Flat-Topped Floating Gate Structure [patent_app_type] => utility [patent_app_number] => 15/921858 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15921858 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/921858
Memory cell with a flat-topped floating gate structure Mar 14, 2018 Issued
Array ( [id] => 13434695 [patent_doc_number] => 20180268890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => REFRESH-FREE TFET MEMORY LATCH [patent_app_type] => utility [patent_app_number] => 15/916585 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11799 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 446 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916585 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916585
REFRESH-FREE TFET MEMORY LATCH Mar 8, 2018 Abandoned
Array ( [id] => 14824985 [patent_doc_number] => 10409499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => NAND flash memory device and system including SLC and MLC write modes [patent_app_type] => utility [patent_app_number] => 15/916551 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916551
NAND flash memory device and system including SLC and MLC write modes Mar 8, 2018 Issued
Array ( [id] => 16172595 [patent_doc_number] => 10714171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => NAND flash memory system storing multi-bit data and read/write control method thereof [patent_app_type] => utility [patent_app_number] => 15/915597 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15915597 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/915597
NAND flash memory system storing multi-bit data and read/write control method thereof Mar 7, 2018 Issued
Array ( [id] => 15640747 [patent_doc_number] => 10593375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Semiconductor memory device with correcting resistances in series with memory array signal lines [patent_app_type] => utility [patent_app_number] => 15/914687 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 10900 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914687 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914687
Semiconductor memory device with correcting resistances in series with memory array signal lines Mar 6, 2018 Issued
Array ( [id] => 14078873 [patent_doc_number] => 20190088324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => MEMORY DEVICE AND VARIABLE RESISTANCE ELEMENT [patent_app_type] => utility [patent_app_number] => 15/911413 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911413 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/911413
Read circuit for a variable resistance memory device Mar 4, 2018 Issued
Array ( [id] => 14078861 [patent_doc_number] => 20190088318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/909535 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909535
MEMORY DEVICE Feb 28, 2018 Abandoned
Array ( [id] => 14691093 [patent_doc_number] => 20190244662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => SUM-OF-PRODUCTS ARRAY FOR NEUROMORPHIC COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 15/887166 [patent_app_country] => US [patent_app_date] => 2018-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887166 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/887166
SUM-OF-PRODUCTS ARRAY FOR NEUROMORPHIC COMPUTING SYSTEM Feb 1, 2018 Abandoned
Array ( [id] => 13419495 [patent_doc_number] => 20180261290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/881664 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881664 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881664
Non-volatile semiconductor storage device with two write modes Jan 25, 2018 Issued
Array ( [id] => 13347165 [patent_doc_number] => 20180225122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => METHOD, SYSTEM, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM FOR ANALYZING ACCESS TO STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/879492 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879492 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879492
Method, system and non-transitory computer-readable storage medium for analyzing access to storage device Jan 24, 2018 Issued
Array ( [id] => 14738507 [patent_doc_number] => 10388663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Wiring line structure of three-dimensional memory device [patent_app_type] => utility [patent_app_number] => 15/878806 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12350 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15878806 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/878806
Wiring line structure of three-dimensional memory device Jan 23, 2018 Issued
Array ( [id] => 14888641 [patent_doc_number] => 10424367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Method and apparatus for decoding command operations for a semiconductor device [patent_app_type] => utility [patent_app_number] => 15/841131 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7185 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841131 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841131
Method and apparatus for decoding command operations for a semiconductor device Dec 12, 2017 Issued
Array ( [id] => 16145325 [patent_doc_number] => 10705732 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => Multiple-apartment aware offlining of devices for disruptive and destructive operations [patent_app_type] => utility [patent_app_number] => 15/840810 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 24139 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840810 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840810
Multiple-apartment aware offlining of devices for disruptive and destructive operations Dec 12, 2017 Issued
Array ( [id] => 14300463 [patent_doc_number] => 10290362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Screening for data retention loss in ferroelectric memories [patent_app_type] => utility [patent_app_number] => 15/837451 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 9400 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837451 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837451
Screening for data retention loss in ferroelectric memories Dec 10, 2017 Issued
Array ( [id] => 16185933 [patent_doc_number] => 10719265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-21 [patent_title] => Centralized, quorum-aware handling of device reservation requests in a storage system [patent_app_type] => utility [patent_app_number] => 15/836652 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 24166 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836652 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/836652
Centralized, quorum-aware handling of device reservation requests in a storage system Dec 7, 2017 Issued
Array ( [id] => 15791109 [patent_doc_number] => 10629284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Semiconductor memory device witih a built-in self test circuit for adjusting a memory device property [patent_app_type] => utility [patent_app_number] => 15/826698 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4784 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826698 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826698
Semiconductor memory device witih a built-in self test circuit for adjusting a memory device property Nov 29, 2017 Issued
Array ( [id] => 15060993 [patent_doc_number] => 10460808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Memory device and programming operation method thereof with different bit line voltages [patent_app_type] => utility [patent_app_number] => 15/793045 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4702 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15793045 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/793045
Memory device and programming operation method thereof with different bit line voltages Oct 24, 2017 Issued
Array ( [id] => 16097863 [patent_doc_number] => 20200202918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => THYRISTORS [patent_app_type] => utility [patent_app_number] => 16/639235 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16639235 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/639235
THYRISTORS Sep 13, 2017 Abandoned
Array ( [id] => 12122119 [patent_doc_number] => 20180005705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'FUSE ELEMENT PROGRAMMING CIRCUIT AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/700910 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6929 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700910
Fuse element programming circuit and method Sep 10, 2017 Issued
Array ( [id] => 12263527 [patent_doc_number] => 20180082723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/694507 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694507
Semiconductor memory apparatus with a write voltage level detection Aug 31, 2017 Issued
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