Search

Jung H. Hur

Examiner (ID: 14455, Phone: (571)272-1870 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1178
Issued Applications
1001
Pending Applications
11
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12713164 [patent_doc_number] => 20180129554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => BITWISE SPARING IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/343308 [patent_app_country] => US [patent_app_date] => 2016-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15343308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/343308
Bitwise sparing in a memory system Nov 3, 2016 Issued
Array ( [id] => 11630621 [patent_doc_number] => 20170140810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME FOR CONTROLLING COLLISION BETWEEN ACCESS OPERATION AND REFRESH OPERATION' [patent_app_type] => utility [patent_app_number] => 15/340345 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340345 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340345
MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME FOR CONTROLLING COLLISION BETWEEN ACCESS OPERATION AND REFRESH OPERATION Oct 31, 2016 Abandoned
Array ( [id] => 12691822 [patent_doc_number] => 20180122440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => CLOCKED COMMANDS TIMING ADJUSTMENTS METHOD IN SYNCHRONOUS SEMICONDUCTOR INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/337979 [patent_app_country] => US [patent_app_date] => 2016-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15337979 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/337979
Clocked commands timing adjustments method in synchronous semiconductor integrated circuits Oct 27, 2016 Issued
Array ( [id] => 12331494 [patent_doc_number] => 09946491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Memory erase method, memory control circuit unit and memory storage apparatus, including an erase index table and mother-child physical erasing units [patent_app_type] => utility [patent_app_number] => 15/333196 [patent_app_country] => US [patent_app_date] => 2016-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 8548 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15333196 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/333196
Memory erase method, memory control circuit unit and memory storage apparatus, including an erase index table and mother-child physical erasing units Oct 24, 2016 Issued
Array ( [id] => 14798189 [patent_doc_number] => 10402098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Nonvolatile memory apparatus and verification write method thereof for reducing program time [patent_app_type] => utility [patent_app_number] => 15/275623 [patent_app_country] => US [patent_app_date] => 2016-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6018 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275623 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/275623
Nonvolatile memory apparatus and verification write method thereof for reducing program time Sep 25, 2016 Issued
Array ( [id] => 11353444 [patent_doc_number] => 20160372184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'Programming Schemes for Multi-Level Analog Memory Cells' [patent_app_type] => utility [patent_app_number] => 15/256992 [patent_app_country] => US [patent_app_date] => 2016-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15256992 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/256992
Programming schemes for multi-level analog memory cells Sep 5, 2016 Issued
Array ( [id] => 11983405 [patent_doc_number] => 20170287560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF WITH A CONNECTION CONTROL TRANSISTOR OPERATION VOLTAGE ADJUSTED' [patent_app_type] => utility [patent_app_number] => 15/250841 [patent_app_country] => US [patent_app_date] => 2016-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15250841 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/250841
Semiconductor memory device and operating method thereof with a connection control transistor operation voltage adjusted Aug 28, 2016 Issued
Array ( [id] => 11989369 [patent_doc_number] => 20170293524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'DATA STORAGE DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/246152 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15246152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/246152
Data storage device and operating method thereof including read error correction Aug 23, 2016 Issued
Array ( [id] => 13006145 [patent_doc_number] => 10026747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Non-volatile memory device with first gate structure in memory cell region and second gate structure in peripheral circuit region and non-volatile memory system including the same [patent_app_type] => utility [patent_app_number] => 15/239121 [patent_app_country] => US [patent_app_date] => 2016-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 15293 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15239121 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/239121
Non-volatile memory device with first gate structure in memory cell region and second gate structure in peripheral circuit region and non-volatile memory system including the same Aug 16, 2016 Issued
Array ( [id] => 11959160 [patent_doc_number] => 20170263312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'MEMORY SYSTEM AND METHOD OF CONTROLLING THEREOF' [patent_app_type] => utility [patent_app_number] => 15/238087 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 17349 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15238087 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/238087
Memory system storing 4-bit data in each memory cell and method of controlling thereof including soft bit information Aug 15, 2016 Issued
Array ( [id] => 11459801 [patent_doc_number] => 20170053707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'Memory System with Small Size Antifuse Circuit Capable of Voltage Boost' [patent_app_type] => utility [patent_app_number] => 15/233970 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7759 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233970 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/233970
Memory system with small size antifuse circuit capable of voltage boost Aug 10, 2016 Issued
Array ( [id] => 11516344 [patent_doc_number] => 20170083418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'HANDLING DEFECTIVE NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 15/235084 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5868 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235084 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/235084
Handling defective non-volatile memory Aug 10, 2016 Issued
Array ( [id] => 11739997 [patent_doc_number] => 09704589 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-11 [patent_title] => 'Folding circuit and nonvolatile memory devices' [patent_app_type] => utility [patent_app_number] => 15/230952 [patent_app_country] => US [patent_app_date] => 2016-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11203 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15230952 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/230952
Folding circuit and nonvolatile memory devices Aug 7, 2016 Issued
Array ( [id] => 11273520 [patent_doc_number] => 20160336068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'MEMORY DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/219773 [patent_app_country] => US [patent_app_date] => 2016-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 25879 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15219773 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/219773
Memory device with a driving circuit comprising transistors each having two gate electrodes and an oxide semiconductor layer Jul 25, 2016 Issued
Array ( [id] => 12120851 [patent_doc_number] => 20180004438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'METHOD AND APPARATUS TO PROVIDE BOTH STORAGE MODE AND MEMORY MODE ACCESS TO NON-VOLATILE MEMORY WITHIN A SOLID STATE DRIVE' [patent_app_type] => utility [patent_app_number] => 15/200933 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6992 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15200933 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/200933
Method and apparatus to provide both storage mode and memory mode access to non-volatile memory within a solid state drive Jun 30, 2016 Issued
Array ( [id] => 13681941 [patent_doc_number] => 20160379707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => CROSS POINT MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/191983 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191983 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/191983
CROSS POINT MEMORY DEVICE Jun 23, 2016 Abandoned
Array ( [id] => 11665964 [patent_doc_number] => 20170154682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'MEMORY SYSTEM AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/099369 [patent_app_country] => US [patent_app_date] => 2016-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 20732 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15099369 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/099369
MEMORY SYSTEM AND OPERATION METHOD THEREOF Apr 13, 2016 Abandoned
Array ( [id] => 11622878 [patent_doc_number] => 20170133065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'LATCH CIRCUIT AND DOUBLE DATA RATE DECODING DEVICE BASED ON THE SAME' [patent_app_type] => utility [patent_app_number] => 15/097721 [patent_app_country] => US [patent_app_date] => 2016-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6644 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15097721 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/097721
Double data rate decoding device with edge-triggered shifting latch stages Apr 12, 2016 Issued
Array ( [id] => 12174619 [patent_doc_number] => 09892765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Circuit for injecting compensating charge in a bias line' [patent_app_type] => utility [patent_app_number] => 15/095189 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4412 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095189 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095189
Circuit for injecting compensating charge in a bias line Apr 10, 2016 Issued
Array ( [id] => 11607766 [patent_doc_number] => 20170125069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING MULTIPLE PLANES' [patent_app_type] => utility [patent_app_number] => 15/093973 [patent_app_country] => US [patent_app_date] => 2016-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15093973 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/093973
SEMICONDUCTOR DEVICE INCLUDING MULTIPLE PLANES Apr 7, 2016 Abandoned
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