Jung H. Hur

Array ( [id] => 17752460 [patent_doc_number] => 20220230665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/716295 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19704728 [patent_doc_number] => 12198774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Memory device sideband systems and methods [patent_app_type] => utility [patent_app_number] => 17/710601 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7681 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18679513 [patent_doc_number] => 20230317169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => NON-VOLATILE MEMORY WITH ZONED CONTROL OF PROGRAMMING [patent_app_type] => utility [patent_app_number] => 17/709762 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18380499 [patent_doc_number] => 20230155589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => CHIP INTERFACE CIRCUIT AND CHIP [patent_app_type] => utility [patent_app_number] => 17/703198 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18696095 [patent_doc_number] => 20230326526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => DYNAMIC INTERFERENCE COMPENSATION FOR SOFT DECODING IN NON-VOLATILE MEMORY STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 17/702359 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17917202 [patent_doc_number] => 20220319598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SINGLE POLY, FLOATING GATE, FEW TIME PROGRAMMABLE NON-VOLATILE MEMORY DEVICE AND BIASING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/697846 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17963380 [patent_doc_number] => 20220343961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => MEMORY DEVICES AND OPERATION METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/695941 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17691829 [patent_doc_number] => 20220199122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => MEMORY SYSTEM STORAGE DEVICE WITH PATH CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/694946 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18631485 [patent_doc_number] => 20230290387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS [patent_app_type] => utility [patent_app_number] => 17/654295 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19341289 [patent_doc_number] => 12051484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Memory device with adjustable delay propagation of a control signal to different page buffer driver groups [patent_app_type] => utility [patent_app_number] => 17/654108 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13577 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18751324 [patent_doc_number] => 11810642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Memory device including defective column addresses stored in ascending order [patent_app_type] => utility [patent_app_number] => 17/687244 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 10795 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18585710 [patent_doc_number] => 20230267974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => READ OPERATIONS FOR A MEMORY ARRAY AND REGISTER [patent_app_type] => utility [patent_app_number] => 17/652233 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17652233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19539211 [patent_doc_number] => 12131766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Memory array with multiplexed select lines and two transistor memory cells [patent_app_type] => utility [patent_app_number] => 17/675686 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 14682 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19399522 [patent_doc_number] => 12073908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => On-die heater devices for memory devices and memory modules [patent_app_type] => utility [patent_app_number] => 17/675707 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 11696 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18572740 [patent_doc_number] => 20230263078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => MEMORY DEVICE, METHOD FOR CONFIGURING MEMORY CELL IN N-BIT MEMORY UNIT, AND MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/672695 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17795314 [patent_doc_number] => 20220254406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => NON-VOLATILE MEMORY CIRCUIT, SEMICONDUCTOR DEVICE, AND METHOD OF READING NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/592044 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17592044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18532962 [patent_doc_number] => 20230238037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => CONTENT ADDRESSABLE MEMORY DEVICE AND METHOD FOR DATA SEARCHING AND COMPARING THEREOF [patent_app_type] => utility [patent_app_number] => 17/583254 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583254 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19328613 [patent_doc_number] => 12046302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Edge word line concurrent programming with verify for memory apparatus with on-pitch semi-circle drain side select gate technology [patent_app_type] => utility [patent_app_number] => 17/557492 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 16730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17536441 [patent_doc_number] => 20220115050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => Memory Sensing Circuit and Method for Using the Same [patent_app_type] => utility [patent_app_number] => 17/557387 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17536456 [patent_doc_number] => 20220115065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => RAMP-BASED BIASING IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/556702 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556702 [rel_patent_id] =>[rel_patent_doc_number] =>)