Search

Junghwa M. Im

Examiner (ID: 14719)

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
529
Issued Applications
282
Pending Applications
10
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4583228 [patent_doc_number] => 07834437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Semiconductor package with passive elements' [patent_app_type] => utility [patent_app_number] => 11/777346 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3140 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/834/07834437.pdf [firstpage_image] =>[orig_patent_app_number] => 11777346 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/777346
Semiconductor package with passive elements Jul 12, 2007 Issued
Array ( [id] => 5307586 [patent_doc_number] => 20090014867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'SEAL RING FOR GLASS WALL MICROELECTRONICS PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/775735 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2391 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20090014867.pdf [firstpage_image] =>[orig_patent_app_number] => 11775735 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775735
SEAL RING FOR GLASS WALL MICROELECTRONICS PACKAGE Jul 9, 2007 Abandoned
Array ( [id] => 4660962 [patent_doc_number] => 20080251869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'PHOTOSENSITIVE CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/773516 [patent_app_country] => US [patent_app_date] => 2007-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1865 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20080251869.pdf [firstpage_image] =>[orig_patent_app_number] => 11773516 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/773516
PHOTOSENSITIVE CHIP PACKAGE Jul 4, 2007 Abandoned
Array ( [id] => 5346230 [patent_doc_number] => 20090001591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'REDUCING RESISTIVITY IN METAL INTERCONNECTS BY COMPRESSIVE STRAINING' [patent_app_type] => utility [patent_app_number] => 11/771476 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3811 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20090001591.pdf [firstpage_image] =>[orig_patent_app_number] => 11771476 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/771476
REDUCING RESISTIVITY IN METAL INTERCONNECTS BY COMPRESSIVE STRAINING Jun 28, 2007 Abandoned
Array ( [id] => 4648844 [patent_doc_number] => 20080036099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Method for producing a component and device having a component' [patent_app_type] => utility [patent_app_number] => 11/770836 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2411 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20080036099.pdf [firstpage_image] =>[orig_patent_app_number] => 11770836 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/770836
Method for producing a component and device having a component Jun 28, 2007 Issued
Array ( [id] => 23345 [patent_doc_number] => 07800211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Stackable package by using internal stacking modules' [patent_app_type] => utility [patent_app_number] => 11/771086 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3785 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/800/07800211.pdf [firstpage_image] =>[orig_patent_app_number] => 11771086 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/771086
Stackable package by using internal stacking modules Jun 28, 2007 Issued
Array ( [id] => 4919354 [patent_doc_number] => 20080067666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'CIRCUIT BOARD STRUCTURE WITH EMBEDDED SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/771345 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3571 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20080067666.pdf [firstpage_image] =>[orig_patent_app_number] => 11771345 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/771345
CIRCUIT BOARD STRUCTURE WITH EMBEDDED SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME Jun 28, 2007 Abandoned
Array ( [id] => 8702023 [patent_doc_number] => 08395246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Two-sided die in a four-sided leadframe based package' [patent_app_type] => utility [patent_app_number] => 11/770066 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4729 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11770066 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/770066
Two-sided die in a four-sided leadframe based package Jun 27, 2007 Issued
Array ( [id] => 4667220 [patent_doc_number] => 20080042280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Semiconductor chip structure' [patent_app_type] => utility [patent_app_number] => 11/769736 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 38525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20080042280.pdf [firstpage_image] =>[orig_patent_app_number] => 11769736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769736
Semiconductor chip structure Jun 27, 2007 Issued
Array ( [id] => 5346239 [patent_doc_number] => 20090001600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'ELECTRONIC DEVICE INCLUDING A PLURALITY OF SINGULATED DIE AND METHODS OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/770295 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20090001600.pdf [firstpage_image] =>[orig_patent_app_number] => 11770295 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/770295
Process of forming an electronic device including a plurality of singulated die Jun 27, 2007 Issued
Array ( [id] => 4958080 [patent_doc_number] => 20080272504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Package-in-Package Using Through-Hole via Die on Saw Streets' [patent_app_type] => utility [patent_app_number] => 11/768825 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 6544 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20080272504.pdf [firstpage_image] =>[orig_patent_app_number] => 11768825 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/768825
Package-in-package using through-hole via die on saw streets Jun 25, 2007 Issued
Array ( [id] => 5208214 [patent_doc_number] => 20070246798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Inductor Energy Loss Reduction Techniques' [patent_app_type] => utility [patent_app_number] => 11/767836 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4581 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20070246798.pdf [firstpage_image] =>[orig_patent_app_number] => 11767836 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/767836
Inductor energy loss reduction techniques Jun 24, 2007 Issued
Array ( [id] => 7550602 [patent_doc_number] => 08062934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Integrated circuit package system with ground bonds' [patent_app_type] => utility [patent_app_number] => 11/766785 [patent_app_country] => US [patent_app_date] => 2007-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 10886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/062/08062934.pdf [firstpage_image] =>[orig_patent_app_number] => 11766785 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/766785
Integrated circuit package system with ground bonds Jun 20, 2007 Issued
Array ( [id] => 8329169 [patent_doc_number] => 08237271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Direct edge connection for multi-chip integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/765055 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5431 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11765055 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/765055
Direct edge connection for multi-chip integrated circuits Jun 18, 2007 Issued
Array ( [id] => 4691223 [patent_doc_number] => 20080083993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Gold-Tin Solder Joints Having Reduced Embrittlement' [patent_app_type] => utility [patent_app_number] => 11/765286 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20080083993.pdf [firstpage_image] =>[orig_patent_app_number] => 11765286 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/765286
Gold-Tin Solder Joints Having Reduced Embrittlement Jun 18, 2007 Abandoned
Array ( [id] => 8642488 [patent_doc_number] => 08367471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/764066 [patent_app_country] => US [patent_app_date] => 2007-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4496 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11764066 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764066
Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices Jun 14, 2007 Issued
Array ( [id] => 4795344 [patent_doc_number] => 20080006930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/763776 [patent_app_country] => US [patent_app_date] => 2007-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4752 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20080006930.pdf [firstpage_image] =>[orig_patent_app_number] => 11763776 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/763776
SEMICONDUCTOR PACKAGE Jun 14, 2007 Abandoned
Array ( [id] => 8435992 [patent_doc_number] => 08283763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Power semiconductor module and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/762276 [patent_app_country] => US [patent_app_date] => 2007-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 4981 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11762276 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/762276
Power semiconductor module and fabrication method thereof Jun 12, 2007 Issued
Array ( [id] => 5228265 [patent_doc_number] => 20070290372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING WIRE LOOP AND METHOD AND APPARATUS FOR MANUFACTURING THE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/761306 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20070290372.pdf [firstpage_image] =>[orig_patent_app_number] => 11761306 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/761306
SEMICONDUCTOR DEVICE HAVING WIRE LOOP AND METHOD AND APPARATUS FOR MANUFACTURING THE SEMICONDUCTOR DEVICE Jun 10, 2007 Abandoned
Array ( [id] => 4949180 [patent_doc_number] => 20080305306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'SEMICONDUCTOR MOLDED PANEL HAVING REDUCED WARPAGE' [patent_app_type] => utility [patent_app_number] => 11/759486 [patent_app_country] => US [patent_app_date] => 2007-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3748 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0305/20080305306.pdf [firstpage_image] =>[orig_patent_app_number] => 11759486 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/759486
SEMICONDUCTOR MOLDED PANEL HAVING REDUCED WARPAGE Jun 6, 2007 Abandoned
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