Search

Junghwa M. Im

Examiner (ID: 10638)

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
529
Issued Applications
282
Pending Applications
10
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5008184 [patent_doc_number] => 20070278661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/464666 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20070278661.pdf [firstpage_image] =>[orig_patent_app_number] => 11464666 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464666
CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF Aug 14, 2006 Abandoned
Array ( [id] => 91882 [patent_doc_number] => 07732253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-08 [patent_title] => 'Flip-chip assembly with improved interconnect' [patent_app_type] => utility [patent_app_number] => 11/464306 [patent_app_country] => US [patent_app_date] => 2006-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732253.pdf [firstpage_image] =>[orig_patent_app_number] => 11464306 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464306
Flip-chip assembly with improved interconnect Aug 13, 2006 Issued
Array ( [id] => 5245222 [patent_doc_number] => 20070241456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Conductive structure for electronic device' [patent_app_type] => utility [patent_app_number] => 11/498146 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 4927 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20070241456.pdf [firstpage_image] =>[orig_patent_app_number] => 11498146 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498146
Conductive structure for electronic device Aug 2, 2006 Abandoned
Array ( [id] => 5640457 [patent_doc_number] => 20060278912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'SELECTIVE POLYSILICON STUD GROWTH' [patent_app_type] => utility [patent_app_number] => 11/461195 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5668 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20060278912.pdf [firstpage_image] =>[orig_patent_app_number] => 11461195 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461195
SELECTIVE POLYSILICON STUD GROWTH Jul 30, 2006 Abandoned
Array ( [id] => 7811548 [patent_doc_number] => 08134080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Wired circuit board' [patent_app_type] => utility [patent_app_number] => 11/477935 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5671 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/134/08134080.pdf [firstpage_image] =>[orig_patent_app_number] => 11477935 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/477935
Wired circuit board Jun 29, 2006 Issued
Array ( [id] => 5094863 [patent_doc_number] => 20070116472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Package for optical transceiver module' [patent_app_type] => utility [patent_app_number] => 11/477896 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3612 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20070116472.pdf [firstpage_image] =>[orig_patent_app_number] => 11477896 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/477896
Package for optical transceiver module Jun 27, 2006 Abandoned
Array ( [id] => 4433528 [patent_doc_number] => 07968998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-28 [patent_title] => 'Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package' [patent_app_type] => utility [patent_app_number] => 11/425505 [patent_app_country] => US [patent_app_date] => 2006-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 15861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/968/07968998.pdf [firstpage_image] =>[orig_patent_app_number] => 11425505 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/425505
Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package Jun 20, 2006 Issued
Array ( [id] => 5228225 [patent_doc_number] => 20070290332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Stacking structure of chip package' [patent_app_type] => utility [patent_app_number] => 11/453105 [patent_app_country] => US [patent_app_date] => 2006-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2405 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20070290332.pdf [firstpage_image] =>[orig_patent_app_number] => 11453105 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/453105
Stacking structure of chip package Jun 14, 2006 Abandoned
Array ( [id] => 5780233 [patent_doc_number] => 20060202328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Memory module and memory configuration with stub-free signal lines and distributed capacitive loads' [patent_app_type] => utility [patent_app_number] => 11/431765 [patent_app_country] => US [patent_app_date] => 2006-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20060202328.pdf [firstpage_image] =>[orig_patent_app_number] => 11431765 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/431765
Memory module and memory configuration with stub-free signal lines and distributed capacitive loads May 9, 2006 Abandoned
Array ( [id] => 5683079 [patent_doc_number] => 20060199349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Method and system for providing a power lateral PNP transistor using a buried power buss\n' [patent_app_type] => utility [patent_app_number] => 11/429382 [patent_app_country] => US [patent_app_date] => 2006-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7753 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199349.pdf [firstpage_image] =>[orig_patent_app_number] => 11429382 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/429382
Method and system for providing a power lateral PNP transistor using a buried power bussn May 4, 2006 Abandoned
Array ( [id] => 9010045 [patent_doc_number] => 08525347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Method for producing chip stacks, and associated chip stacks' [patent_app_type] => utility [patent_app_number] => 11/416712 [patent_app_country] => US [patent_app_date] => 2006-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4364 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11416712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/416712
Method for producing chip stacks, and associated chip stacks May 2, 2006 Issued
Array ( [id] => 5329130 [patent_doc_number] => 20090109607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Housing for an Electronic Device and Sealing Ring for a Housing' [patent_app_type] => utility [patent_app_number] => 11/886661 [patent_app_country] => US [patent_app_date] => 2006-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1458 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109607.pdf [firstpage_image] =>[orig_patent_app_number] => 11886661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/886661
Housing for an electronic device and sealing ring for a housing Mar 13, 2006 Issued
Array ( [id] => 5256794 [patent_doc_number] => 20070210426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Gold-bumped interposer for vertically integrated semiconductor system' [patent_app_type] => utility [patent_app_number] => 11/370265 [patent_app_country] => US [patent_app_date] => 2006-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210426.pdf [firstpage_image] =>[orig_patent_app_number] => 11370265 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/370265
Gold-bumped interposer for vertically integrated semiconductor system Mar 6, 2006 Abandoned
Array ( [id] => 5180747 [patent_doc_number] => 20070052089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Adhesive film having multiple filler distribution and method of manufacturing the same, and chip stack package having the adhesive film and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/366456 [patent_app_country] => US [patent_app_date] => 2006-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3685 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20070052089.pdf [firstpage_image] =>[orig_patent_app_number] => 11366456 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/366456
Adhesive film having multiple filler distribution and method of manufacturing the same, and chip stack package having the adhesive film and method of manufacturing the same Mar 2, 2006 Abandoned
Array ( [id] => 7504891 [patent_doc_number] => 08035225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Semiconductor chip assembly and fabrication method therefor' [patent_app_type] => utility [patent_app_number] => 11/722925 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 6957 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/035/08035225.pdf [firstpage_image] =>[orig_patent_app_number] => 11722925 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/722925
Semiconductor chip assembly and fabrication method therefor Dec 27, 2005 Issued
Array ( [id] => 4810729 [patent_doc_number] => 20080191360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Adhesive Strip Conductor on an Insulating Layer' [patent_app_type] => utility [patent_app_number] => 11/884231 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2141 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191360.pdf [firstpage_image] =>[orig_patent_app_number] => 11884231 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/884231
Adhesive Strip Conductor on an Insulating Layer Dec 21, 2005 Abandoned
Array ( [id] => 4431804 [patent_doc_number] => 07968371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Semiconductor package system with cavity substrate' [patent_app_type] => utility [patent_app_number] => 11/164336 [patent_app_country] => US [patent_app_date] => 2005-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 18 [patent_no_of_words] => 3757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/968/07968371.pdf [firstpage_image] =>[orig_patent_app_number] => 11164336 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/164336
Semiconductor package system with cavity substrate Nov 17, 2005 Issued
Array ( [id] => 4980643 [patent_doc_number] => 20070085199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM USING ETCHED LEADFRAME' [patent_app_type] => utility [patent_app_number] => 11/163305 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20070085199.pdf [firstpage_image] =>[orig_patent_app_number] => 11163305 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163305
Integrated circuit package system using etched leadframe Oct 12, 2005 Issued
Array ( [id] => 4980652 [patent_doc_number] => 20070085208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/163285 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2524 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20070085208.pdf [firstpage_image] =>[orig_patent_app_number] => 11163285 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163285
INTERCONNECT STRUCTURE Oct 12, 2005 Abandoned
Array ( [id] => 915401 [patent_doc_number] => 07327018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-05 [patent_title] => 'Chip package structure, package substrate and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/163276 [patent_app_country] => US [patent_app_date] => 2005-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3624 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/327/07327018.pdf [firstpage_image] =>[orig_patent_app_number] => 11163276 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163276
Chip package structure, package substrate and manufacturing method thereof Oct 11, 2005 Issued
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