Search

Justin R. Knapp

Examiner (ID: 122, Phone: (571)270-3008 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2182, 2112, 2183
Total Applications
856
Issued Applications
683
Pending Applications
69
Abandoned Applications
122

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17340144 [patent_doc_number] => 20220006475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => PERFORMANCE ENHANCEMENT OF POLAR CODES FOR SHORT FRAME LENGTHS CONSIDERING ERROR PROPAGATION EFFECTS [patent_app_type] => utility [patent_app_number] => 17/296261 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17296261 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/296261
PERFORMANCE ENHANCEMENT OF POLAR CODES FOR SHORT FRAME LENGTHS CONSIDERING ERROR PROPAGATION EFFECTS Oct 17, 2019 Abandoned
Array ( [id] => 15773049 [patent_doc_number] => 20200117542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => MULTIPLE NODE REPAIR USING HIGH RATE MINIMUM STORAGE REGENERATION ERASURE CODE [patent_app_type] => utility [patent_app_number] => 16/599298 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599298 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599298
Multiple node repair using high rate minimum storage regeneration erasure code Oct 10, 2019 Issued
Array ( [id] => 15444425 [patent_doc_number] => 20200036396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => APPARATUSES AND METHODS FOR PIPELINING MEMORY OPERATIONS WITH ERROR CORRECTION CODING [patent_app_type] => utility [patent_app_number] => 16/593479 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16593479 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/593479
Apparatuses and methods for pipelining memory operations with error correction coding Oct 3, 2019 Issued
Array ( [id] => 15416583 [patent_doc_number] => 20200028614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => METHOD FOR POLAR CODING IN COMMUNICATION NETWORK [patent_app_type] => utility [patent_app_number] => 16/586385 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586385 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586385
Method for polar coding in communication network Sep 26, 2019 Issued
Array ( [id] => 16486061 [patent_doc_number] => 20200379666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => TEMPORARY RELOCATION OF DATA WITHIN LOCAL STORAGE OF A DISPERSED STORAGE NETWORK [patent_app_type] => utility [patent_app_number] => 16/571464 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571464 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/571464
Temporary relocation of data within local storage of a dispersed storage network Sep 15, 2019 Issued
Array ( [id] => 16638597 [patent_doc_number] => 10917119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Data storage system and associated data storing method for reducing data error rate [patent_app_type] => utility [patent_app_number] => 16/568221 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4330 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568221
Data storage system and associated data storing method for reducing data error rate Sep 10, 2019 Issued
Array ( [id] => 15333885 [patent_doc_number] => 20200007272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => TRANSMITTING DEVICE AND TRANSMITTING METHOD [patent_app_type] => utility [patent_app_number] => 16/561308 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 43769 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561308 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561308
Transmitting device with erasure correction coding and transmitting method with erasure correction coding Sep 4, 2019 Issued
Array ( [id] => 19212206 [patent_doc_number] => 12001268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Reducing unitary error in a quantum computation system [patent_app_type] => utility [patent_app_number] => 17/264773 [patent_app_country] => US [patent_app_date] => 2019-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 16875 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17264773 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/264773
Reducing unitary error in a quantum computation system Aug 11, 2019 Issued
Array ( [id] => 17138258 [patent_doc_number] => 11139831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Fast fail support for error correction in non-volatile memory [patent_app_type] => utility [patent_app_number] => 16/526784 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526784
Fast fail support for error correction in non-volatile memory Jul 29, 2019 Issued
Array ( [id] => 17454863 [patent_doc_number] => 11269722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Apparatus for diagnosing memory system and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/524673 [patent_app_country] => US [patent_app_date] => 2019-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 21818 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16524673 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/524673
Apparatus for diagnosing memory system and operating method thereof Jul 28, 2019 Issued
Array ( [id] => 16972365 [patent_doc_number] => 11068337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Data processing apparatus that disconnects control circuit from error detection circuit and diagnosis method [patent_app_type] => utility [patent_app_number] => 16/523031 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9604 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523031 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523031
Data processing apparatus that disconnects control circuit from error detection circuit and diagnosis method Jul 25, 2019 Issued
Array ( [id] => 15121057 [patent_doc_number] => 20190347162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => METHOD AND SYSTEM UTILIZING QUINTUPLE PARITY TO PROVIDE FAULT TOLERANCE [patent_app_type] => utility [patent_app_number] => 16/521256 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521256 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521256
Method and system utilizing quintuple parity to provide fault tolerance Jul 23, 2019 Issued
Array ( [id] => 19109301 [patent_doc_number] => 11962423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Method and apparatus, UE, and base station for scheduling-free retransmission for a code block group [patent_app_type] => utility [patent_app_number] => 17/267338 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 11856 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17267338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/267338
Method and apparatus, UE, and base station for scheduling-free retransmission for a code block group Jul 18, 2019 Issued
Array ( [id] => 15094251 [patent_doc_number] => 20190341937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => METHOD FOR CONTROLLING STORAGE DEVICE WITH AID OF ERROR CORRECTION AND ASSOCIATED APPARATUS [patent_app_type] => utility [patent_app_number] => 16/516268 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516268 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516268
Method for controlling storage device with aid of error correction and associated apparatus Jul 18, 2019 Issued
Array ( [id] => 18248168 [patent_doc_number] => 11604757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Processing data in memory using an FPGA [patent_app_type] => utility [patent_app_number] => 16/513764 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513764
Processing data in memory using an FPGA Jul 16, 2019 Issued
Array ( [id] => 17181926 [patent_doc_number] => 11159180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Method and apparatus for constructing a polar code [patent_app_type] => utility [patent_app_number] => 16/979749 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 10409 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16979749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/979749
Method and apparatus for constructing a polar code Jun 25, 2019 Issued
Array ( [id] => 14970387 [patent_doc_number] => 20190312672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => CHANNEL CODING METHOD OF VARIABLE LENGTH INFORMATION USING BLOCK CODE [patent_app_type] => utility [patent_app_number] => 16/450216 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 804 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/450216
Channel coding method of variable length information using block code Jun 23, 2019 Issued
Array ( [id] => 16487462 [patent_doc_number] => 20200381071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => SYSTEMS AND METHODS FOR SIMULATED DEVICE TESTING USING A MEMORY-BASED COMMUNICATION PROTOCOL [patent_app_type] => utility [patent_app_number] => 16/430284 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430284
Systems and methods for simulated device testing using a memory-based communication protocol Jun 2, 2019 Issued
Array ( [id] => 16486060 [patent_doc_number] => 20200379665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => TEMPORARY RELOCATION OF DATA WITHIN LOCAL STORAGE OF A DISPERSED STORAGE NETWORK [patent_app_type] => utility [patent_app_number] => 16/429517 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/429517
Temporary relocation of data within local storage of a dispersed storage network Jun 2, 2019 Issued
Array ( [id] => 14872567 [patent_doc_number] => 20190286525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => DEFERRED REBUILDING WITH ALTERNATE STORAGE LOCATIONS [patent_app_type] => utility [patent_app_number] => 16/427420 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16427420 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/427420
Deferred rebuilding with alternate storage locations May 30, 2019 Issued
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