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Jyoti Mehta

Examiner (ID: 12086, Phone: (571)270-3995 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2183, 2182
Total Applications
331
Issued Applications
233
Pending Applications
17
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20624125 [patent_doc_number] => 12591633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Computational memory [patent_app_type] => utility [patent_app_number] => 18/830123 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 40 [patent_no_of_words] => 7770 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/830123
Computational memory Sep 9, 2024 Issued
Array ( [id] => 19878480 [patent_doc_number] => 20250110737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/827415 [patent_app_country] => US [patent_app_date] => 2024-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18827415 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/827415
Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions Sep 5, 2024 Issued
Array ( [id] => 19530358 [patent_doc_number] => 20240354260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SORTING VECTOR ELEMENTS USING A COUNT VALUE [patent_app_type] => utility [patent_app_number] => 18/762987 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762987 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762987
Sorting vector elements using a count value Jul 2, 2024 Issued
Array ( [id] => 19660782 [patent_doc_number] => 20240427847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTS [patent_app_type] => utility [patent_app_number] => 18/757003 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757003 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/757003
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTS Jun 26, 2024 Pending
Array ( [id] => 20281685 [patent_doc_number] => 20250306927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => VECTOR MASK BUFFERS IN A VECTOR INSTRUCTION EXECUTION PIPELINE [patent_app_type] => utility [patent_app_number] => 18/749599 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749599 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749599
Vector mask buffers in a vector instruction execution pipeline Jun 19, 2024 Issued
Array ( [id] => 19451029 [patent_doc_number] => 20240311159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => Reducing Overhead In Processor Array Searching [patent_app_type] => utility [patent_app_number] => 18/670932 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670932
Reducing Overhead In Processor Array Searching May 21, 2024 Issued
Array ( [id] => 20070651 [patent_doc_number] => 20250208873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => HIGH LEVEL GRAPH COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/663946 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663946
High level graph computing system May 13, 2024 Issued
Array ( [id] => 20351459 [patent_doc_number] => 20250348311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => VECTOR PROCESSOR TILE ARRAY WITH INPUT AND OUTPUT STREAMS [patent_app_type] => utility [patent_app_number] => 18/662955 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662955 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662955
Vector processor tile array with input and output streams May 12, 2024 Issued
Array ( [id] => 20563999 [patent_doc_number] => 12566608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Methods and systems for data transfer [patent_app_type] => utility [patent_app_number] => 18/660683 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3666 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660683 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660683
Methods and systems for data transfer May 9, 2024 Issued
Array ( [id] => 20234275 [patent_doc_number] => 20250291594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => FUSED COMPARISON ADD INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/606865 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606865 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606865
Fused comparison add instructions Mar 14, 2024 Issued
Array ( [id] => 19347313 [patent_doc_number] => 20240256276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE [patent_app_type] => utility [patent_app_number] => 18/432317 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432317 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432317
Systems, methods, and apparatuses for tile store Feb 4, 2024 Issued
Array ( [id] => 20137967 [patent_doc_number] => 20250245011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => BRANCH PREDICTION [patent_app_type] => utility [patent_app_number] => 18/428320 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428320 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428320
Branch prediction based on sampled values Jan 30, 2024 Issued
Array ( [id] => 19558469 [patent_doc_number] => 20240370261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => Systems and Methods Providing Pause for Interrupts and Shared Memory Access [patent_app_type] => utility [patent_app_number] => 18/426174 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426174 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426174
Systems and Methods Providing Pause for Interrupts and Shared Memory Access Jan 28, 2024 Pending
Array ( [id] => 20624031 [patent_doc_number] => 12591539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Rearranging data among processing elements of computational memory [patent_app_type] => utility [patent_app_number] => 18/424143 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424143 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424143
Rearranging data among processing elements of computational memory Jan 25, 2024 Issued
Array ( [id] => 19434585 [patent_doc_number] => 20240303083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => METHOD AND APPARATUS FOR COMPILING FOR OVERLAPPING INSTRUCTIONS ON MULTIPLE PROCESSORS [patent_app_type] => utility [patent_app_number] => 18/423642 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423642 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423642
METHOD AND APPARATUS FOR COMPILING FOR OVERLAPPING INSTRUCTIONS ON MULTIPLE PROCESSORS Jan 25, 2024 Pending
Array ( [id] => 20507090 [patent_doc_number] => 12541366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Sorting elements in a memory array by comparing element vectors [patent_app_type] => utility [patent_app_number] => 18/534597 [patent_app_country] => US [patent_app_date] => 2023-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 1904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534597 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534597
Sorting elements in a memory array by comparing element vectors Dec 8, 2023 Issued
Array ( [id] => 20564004 [patent_doc_number] => 12566613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Microprocessor with speculative and in-order register sets [patent_app_type] => utility [patent_app_number] => 18/388908 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3979 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/388908
Microprocessor with speculative and in-order register sets Nov 12, 2023 Issued
Array ( [id] => 19878486 [patent_doc_number] => 20250110743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => BRANCH TARGET BUFFER VICTIM CACHE [patent_app_type] => utility [patent_app_number] => 18/374223 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374223 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/374223
BRANCH TARGET BUFFER VICTIM CACHE Sep 27, 2023 Pending
Array ( [id] => 20595248 [patent_doc_number] => 12578964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Prediction data corruption [patent_app_type] => utility [patent_app_number] => 18/459602 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3672 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459602 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/459602
Prediction data corruption Aug 31, 2023 Issued
Array ( [id] => 20528976 [patent_doc_number] => 12547411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Securing conditional speculative instruction execution [patent_app_type] => utility [patent_app_number] => 18/353558 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353558 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/353558
Securing conditional speculative instruction execution Jul 16, 2023 Issued
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