Search

Jyoti Mehta

Examiner (ID: 9002, Phone: (571)270-3995 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2183, 2182
Total Applications
338
Issued Applications
235
Pending Applications
22
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12495222 [patent_doc_number] => 09996359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Fast multi-width instruction issue in parallel slice processor [patent_app_type] => utility [patent_app_number] => 15/093192 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15093192 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/093192
Fast multi-width instruction issue in parallel slice processor Apr 6, 2016 Issued
Array ( [id] => 11989333 [patent_doc_number] => 20170293488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'ROTATIONAL DISPATCH FOR PARALLEL SLICE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/093172 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15093172 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/093172
Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port Apr 6, 2016 Issued
Array ( [id] => 16200617 [patent_doc_number] => 10725780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Convert to zoned format from decimal floating point format [patent_app_type] => utility [patent_app_number] => 15/083362 [patent_app_country] => US [patent_app_date] => 2016-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 17597 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15083362 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/083362
Convert to zoned format from decimal floating point format Mar 28, 2016 Issued
Array ( [id] => 11013190 [patent_doc_number] => 20160210143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT' [patent_app_type] => utility [patent_app_number] => 15/082694 [patent_app_country] => US [patent_app_date] => 2016-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 18062 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15082694 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/082694
Convert to zoned format from decimal floating point format Mar 27, 2016 Issued
Array ( [id] => 11693121 [patent_doc_number] => 20170168836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'OPERATION OF A MULTI-SLICE PROCESSOR WITH SPECULATIVE DATA LOADING' [patent_app_type] => utility [patent_app_number] => 15/049550 [patent_app_country] => US [patent_app_date] => 2016-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5135 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15049550 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/049550
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor Feb 21, 2016 Issued
Array ( [id] => 11693120 [patent_doc_number] => 20170168835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'OPERATION OF A MULTI-SLICE PROCESSOR WITH INSTRUCTION QUEUE PROCESSING' [patent_app_type] => utility [patent_app_number] => 15/046799 [patent_app_country] => US [patent_app_date] => 2016-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5183 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046799 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/046799
Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction Feb 17, 2016 Issued
Array ( [id] => 10793808 [patent_doc_number] => 20160139965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'METHOD AND APPARATUS FOR A HIERARCHICAL SYNCHRONIZATION BARRIER IN A MULTI-NODE SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/006677 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7521 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006677 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006677
Method and apparatus for a hierarchical synchronization barrier in a multi-node system Jan 25, 2016 Issued
Array ( [id] => 11708860 [patent_doc_number] => 20170177359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Instructions and Logic for Lane-Based Strided Scatter Operations' [patent_app_type] => utility [patent_app_number] => 14/977443 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 35873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977443 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977443
Instructions and Logic for Lane-Based Strided Scatter Operations Dec 20, 2015 Abandoned
Array ( [id] => 11708861 [patent_doc_number] => 20170177360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Instructions and Logic for Load-Indices-and-Scatter Operations' [patent_app_type] => utility [patent_app_number] => 14/977445 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 31389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977445 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977445
Instructions and Logic for Load-Indices-and-Scatter Operations Dec 20, 2015 Abandoned
Array ( [id] => 11708849 [patent_doc_number] => 20170177348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Instruction and Logic for Compression and Rotation' [patent_app_type] => utility [patent_app_number] => 14/977293 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 23324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977293 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977293
Instruction and Logic for Compression and Rotation Dec 20, 2015 Abandoned
Array ( [id] => 11708865 [patent_doc_number] => 20170177364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Instruction and Logic for Reoccurring Adjacent Gathers' [patent_app_type] => utility [patent_app_number] => 14/975803 [patent_app_country] => US [patent_app_date] => 2015-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 22780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975803 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/975803
Instruction and Logic for Reoccurring Adjacent Gathers Dec 19, 2015 Abandoned
Array ( [id] => 11708858 [patent_doc_number] => 20170177357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Instruction and Logic for Vector Permute' [patent_app_type] => utility [patent_app_number] => 14/975804 [patent_app_country] => US [patent_app_date] => 2015-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 23104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975804 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/975804
Permutating vector data scattered in a temporary destination into elements of a destination register based on a permutation factor Dec 19, 2015 Issued
Array ( [id] => 11693106 [patent_doc_number] => 20170168821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'OPERATION OF A MULTI-SLICE PROCESSOR WITH SPECULATIVE DATA LOADING' [patent_app_type] => utility [patent_app_number] => 14/969336 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5116 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969336 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/969336
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor Dec 14, 2015 Issued
Array ( [id] => 14202733 [patent_doc_number] => 10268482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction [patent_app_type] => utility [patent_app_number] => 14/969283 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5018 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969283 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/969283
Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction Dec 14, 2015 Issued
Array ( [id] => 11278678 [patent_doc_number] => 09495157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-15 [patent_title] => 'Fingerprint-based branch prediction' [patent_app_type] => utility [patent_app_number] => 14/960535 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4227 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14960535 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/960535
Fingerprint-based branch prediction Dec 6, 2015 Issued
Array ( [id] => 16535177 [patent_doc_number] => 10877777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Enabling virtual calls in a SIMD environment [patent_app_type] => utility [patent_app_number] => 14/877582 [patent_app_country] => US [patent_app_date] => 2015-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4177 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14877582 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/877582
Enabling virtual calls in a SIMD environment Oct 6, 2015 Issued
Array ( [id] => 16957819 [patent_doc_number] => 11061680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Instructions controlling access to shared registers of a multi-threaded processor [patent_app_type] => utility [patent_app_number] => 14/847157 [patent_app_country] => US [patent_app_date] => 2015-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 10231 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 458 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14847157 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/847157
Instructions controlling access to shared registers of a multi-threaded processor Sep 7, 2015 Issued
Array ( [id] => 12194560 [patent_doc_number] => 09898290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Efficiency for coordinated start interpretive execution exit for a multithreaded processor' [patent_app_type] => utility [patent_app_number] => 14/844223 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8892 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844223 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/844223
Efficiency for coordinated start interpretive execution exit for a multithreaded processor Sep 2, 2015 Issued
Array ( [id] => 11445138 [patent_doc_number] => 20170046159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'POWER EFFICIENT FETCH ADAPTATION' [patent_app_type] => utility [patent_app_number] => 14/827262 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8122 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827262 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827262
POWER EFFICIENT FETCH ADAPTATION Aug 13, 2015 Abandoned
Array ( [id] => 10778744 [patent_doc_number] => 20160124900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'COMPARISON-BASED SORT IN AN ARRAY PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/729281 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16143 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14729281 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/729281
Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements Jun 2, 2015 Issued
Menu