Search

Jyoti Mehta

Examiner (ID: 9002, Phone: (571)270-3995 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2183, 2182
Total Applications
338
Issued Applications
235
Pending Applications
22
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10672917 [patent_doc_number] => 20160019062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'INSTRUCTION AND LOGIC FOR ADAPTIVE EVENT-BASED SAMPLING' [patent_app_type] => utility [patent_app_number] => 14/332736 [patent_app_country] => US [patent_app_date] => 2014-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 20809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14332736 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/332736
INSTRUCTION AND LOGIC FOR ADAPTIVE EVENT-BASED SAMPLING Jul 15, 2014 Abandoned
Array ( [id] => 10928005 [patent_doc_number] => 20140331025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'RECONFIGURABLE PROCESSOR AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/269560 [patent_app_country] => US [patent_app_date] => 2014-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5161 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14269560 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/269560
RECONFIGURABLE PROCESSOR AND OPERATION METHOD THEREOF May 4, 2014 Abandoned
Array ( [id] => 10928010 [patent_doc_number] => 20140331031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'RECONFIGURABLE PROCESSOR HAVING CONSTANT STORAGE REGISTER' [patent_app_type] => utility [patent_app_number] => 14/269764 [patent_app_country] => US [patent_app_date] => 2014-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2410 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14269764 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/269764
RECONFIGURABLE PROCESSOR HAVING CONSTANT STORAGE REGISTER May 4, 2014 Abandoned
Array ( [id] => 13240747 [patent_doc_number] => 10133572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Techniques for serialized execution in a SIMD processing system [patent_app_type] => utility [patent_app_number] => 14/268215 [patent_app_country] => US [patent_app_date] => 2014-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8799 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14268215 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/268215
Techniques for serialized execution in a SIMD processing system May 1, 2014 Issued
Array ( [id] => 15106281 [patent_doc_number] => 10474465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Pop stack absolute instruction [patent_app_type] => utility [patent_app_number] => 14/267362 [patent_app_country] => US [patent_app_date] => 2014-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7039 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14267362 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/267362
Pop stack absolute instruction Apr 30, 2014 Issued
Array ( [id] => 9558872 [patent_doc_number] => 20140176584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'REDUCING ENERGY AND INCREASING SPEED BY AN INSTRUCTION SUBSTITUTING SUBSEQUENT INSTRUCTIONS WITH SPECIFIC FUNCTION INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/190131 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4040 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14190131 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/190131
Reducing energy and increasing speed by an instruction substituting subsequent instructions with specific function instruction Feb 25, 2014 Issued
Array ( [id] => 10258080 [patent_doc_number] => 20150143077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'VECTOR PROCESSING ENGINES (VPEs) EMPLOYING MERGING CIRCUITRY IN DATA FLOW PATHS BETWEEN EXECUTION UNITS AND VECTOR DATA MEMORY TO PROVIDE IN-FLIGHT MERGING OF OUTPUT VECTOR DATA STORED TO VECTOR DATA MEMORY, AND RELATED VECTOR PROCESSING INSTRUCTIONS, SYSTEMS, AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/082073 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 55490 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082073 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082073
Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory, and related vector processing instructions, systems, and methods Nov 14, 2013 Issued
Array ( [id] => 9891560 [patent_doc_number] => 08977835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency' [patent_app_type] => utility [patent_app_number] => 14/079875 [patent_app_country] => US [patent_app_date] => 2013-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7536 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14079875 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/079875
Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency Nov 13, 2013 Issued
13/996513 SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING VECTOR PACKED UNARY DECODING USING MASKS Jun 19, 2013 Abandoned
Array ( [id] => 9096415 [patent_doc_number] => 20130275726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'ARITHMETIC PROCESSING APPARATUS AND BRANCH PREDICTION METHOD' [patent_app_type] => utility [patent_app_number] => 13/914002 [patent_app_country] => US [patent_app_date] => 2013-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 18398 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13914002 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/914002
Method for predicting branch target address based on previous prediction Jun 9, 2013 Issued
Array ( [id] => 9200383 [patent_doc_number] => 20130339698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION' [patent_app_type] => utility [patent_app_number] => 13/804524 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8050 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13804524 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/804524
Selectively blocking branch prediction for a predetermined number of instructions Mar 13, 2013 Issued
Array ( [id] => 15399045 [patent_doc_number] => 10540179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Apparatus and method for bonding branch instruction with architectural delay slot [patent_app_type] => utility [patent_app_number] => 13/789467 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1995 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13789467 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/789467
Apparatus and method for bonding branch instruction with architectural delay slot Mar 6, 2013 Issued
Array ( [id] => 9571617 [patent_doc_number] => 20140189330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'OPTIONAL BRANCHES' [patent_app_type] => utility [patent_app_number] => 13/728285 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8893 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13728285 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/728285
OPTIONAL BRANCHES Dec 26, 2012 Abandoned
Array ( [id] => 9563761 [patent_doc_number] => 20140181474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'ATOMIC WRITE AND READ MICROPROCESSOR INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/727282 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727282 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/727282
ATOMIC WRITE AND READ MICROPROCESSOR INSTRUCTIONS Dec 25, 2012 Abandoned
Array ( [id] => 9563764 [patent_doc_number] => 20140181477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'Compressing Execution Cycles For Divergent Execution In A Single Instruction Multiple Data (SIMD) Processor' [patent_app_type] => utility [patent_app_number] => 13/724633 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8681 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724633 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/724633
Compressing execution cycles for divergent execution in a single instruction multiple data (SIMD) processor Dec 20, 2012 Issued
Array ( [id] => 9520486 [patent_doc_number] => 20140156978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'Detecting and Filtering Biased Branches in Global Branch History' [patent_app_type] => utility [patent_app_number] => 13/691049 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3877 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13691049 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/691049
Detecting and Filtering Biased Branches in Global Branch History Nov 29, 2012 Abandoned
Array ( [id] => 10914370 [patent_doc_number] => 20140317389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'COMPUTATIONAL SPRINTING USING MULTIPLE CORES' [patent_app_type] => utility [patent_app_number] => 14/356573 [patent_app_country] => US [patent_app_date] => 2012-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8973 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14356573 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/356573
COMPUTATIONAL SPRINTING USING MULTIPLE CORES Nov 15, 2012 Abandoned
Array ( [id] => 11846385 [patent_doc_number] => 09733939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Physical reference list for tracking physical register sharing' [patent_app_type] => utility [patent_app_number] => 13/631664 [patent_app_country] => US [patent_app_date] => 2012-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5234 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13631664 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/631664
Physical reference list for tracking physical register sharing Sep 27, 2012 Issued
Array ( [id] => 11860810 [patent_doc_number] => 09740493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'System and method of loop vectorization by compressing indexes and data elements from iterations based on a control mask' [patent_app_type] => utility [patent_app_number] => 13/994549 [patent_app_country] => US [patent_app_date] => 2012-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 13715 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13994549 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/994549
System and method of loop vectorization by compressing indexes and data elements from iterations based on a control mask Sep 27, 2012 Issued
Array ( [id] => 9386106 [patent_doc_number] => 20140089589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'BARRIER COLORS' [patent_app_type] => utility [patent_app_number] => 13/629471 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7167 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13629471 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/629471
Processor and method for implementing barrier operation using speculative and architectural color values Sep 26, 2012 Issued
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