Search

Jyoti Mehta

Examiner (ID: 9002, Phone: (571)270-3995 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2183, 2182
Total Applications
338
Issued Applications
235
Pending Applications
22
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11577517 [patent_doc_number] => 09632778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry' [patent_app_type] => utility [patent_app_number] => 13/569363 [patent_app_country] => US [patent_app_date] => 2012-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8216 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13569363 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/569363
Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry Aug 7, 2012 Issued
Array ( [id] => 11577516 [patent_doc_number] => 09632777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry' [patent_app_type] => utility [patent_app_number] => 13/566141 [patent_app_country] => US [patent_app_date] => 2012-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8152 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13566141 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/566141
Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry Aug 2, 2012 Issued
Array ( [id] => 9224943 [patent_doc_number] => 20140019718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'VECTORIZED PATTERN SEARCHING' [patent_app_type] => utility [patent_app_number] => 13/545819 [patent_app_country] => US [patent_app_date] => 2012-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5281 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13545819 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/545819
VECTORIZED PATTERN SEARCHING Jul 9, 2012 Abandoned
Array ( [id] => 9224954 [patent_doc_number] => 20140019729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'Method for Processing Data Sets, a Pipelined Stream Processor for Processing Data Sets, and a Computer Program for Programming a Pipelined Stream Processor' [patent_app_type] => utility [patent_app_number] => 13/545326 [patent_app_country] => US [patent_app_date] => 2012-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8602 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13545326 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/545326
Processing data sets using dedicated logic units to prevent data collision in a pipelined stream processor Jul 9, 2012 Issued
Array ( [id] => 8608653 [patent_doc_number] => 20130013965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'MICROPROCESSOR PROTECTED AGAINST STACK OVERFLOW' [patent_app_type] => utility [patent_app_number] => 13/543673 [patent_app_country] => US [patent_app_date] => 2012-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13543673 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/543673
MICROPROCESSOR PROTECTED AGAINST STACK OVERFLOW Jul 5, 2012 Abandoned
Array ( [id] => 9213908 [patent_doc_number] => 20140013085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'LOW POWER AND HIGH PERFORMANCE PHYSICAL REGISTER FREE LIST IMPLEMENTATION FOR MICROPROCESSORS' [patent_app_type] => utility [patent_app_number] => 13/541351 [patent_app_country] => US [patent_app_date] => 2012-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6430 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13541351 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/541351
System and method for register renaming with register assignment based on an imbalance in free list banks Jul 2, 2012 Issued
Array ( [id] => 9200381 [patent_doc_number] => 20130339696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION' [patent_app_type] => utility [patent_app_number] => 13/524402 [patent_app_country] => US [patent_app_date] => 2012-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13524402 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/524402
Selectively blocking branch prediction for a predetermined number of instructions Jun 14, 2012 Issued
Array ( [id] => 11659162 [patent_doc_number] => 09672164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Methods and systems for transitioning between a user state and a supervisor state based on a next instruction fetch address' [patent_app_type] => utility [patent_app_number] => 13/485078 [patent_app_country] => US [patent_app_date] => 2012-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 12401 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13485078 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/485078
Methods and systems for transitioning between a user state and a supervisor state based on a next instruction fetch address May 30, 2012 Issued
Array ( [id] => 8868109 [patent_doc_number] => 20130151813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'SWITCH SYSTEM FOR DUAL CENTRAL PROCESSING UNITS' [patent_app_type] => utility [patent_app_number] => 13/483061 [patent_app_country] => US [patent_app_date] => 2012-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2854 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13483061 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/483061
SWITCH SYSTEM FOR DUAL CENTRAL PROCESSING UNITS May 29, 2012 Abandoned
Array ( [id] => 11509130 [patent_doc_number] => 09600289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Load-store dependency predictor PC hashing' [patent_app_type] => utility [patent_app_number] => 13/483268 [patent_app_country] => US [patent_app_date] => 2012-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9831 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13483268 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/483268
Load-store dependency predictor PC hashing May 29, 2012 Issued
Array ( [id] => 8511896 [patent_doc_number] => 20120311305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'INFORMATION PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/482630 [patent_app_country] => US [patent_app_date] => 2012-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10248 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13482630 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/482630
Device for offloading instructions and data from primary to secondary data path May 28, 2012 Issued
Array ( [id] => 8504516 [patent_doc_number] => 20120303924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'Stochastic Processing' [patent_app_type] => utility [patent_app_number] => 13/482723 [patent_app_country] => US [patent_app_date] => 2012-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 20315 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13482723 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/482723
Stochastic processing of an information stream by a processing architecture generated by operation of non-deterministic data used to select data processing modules May 28, 2012 Issued
Array ( [id] => 10091900 [patent_doc_number] => 09128725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Load-store dependency predictor content management' [patent_app_type] => utility [patent_app_number] => 13/464647 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9792 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464647 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/464647
Load-store dependency predictor content management May 3, 2012 Issued
Array ( [id] => 11801315 [patent_doc_number] => 09542191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Hardware profiling mechanism to enable page level automatic binary translation' [patent_app_type] => utility [patent_app_number] => 13/993792 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993792 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993792
Hardware profiling mechanism to enable page level automatic binary translation Mar 29, 2012 Issued
Array ( [id] => 9044122 [patent_doc_number] => 20130246761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'REGISTER SHARING IN AN EXTENDED PROCESSOR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/418359 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13418359 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/418359
REGISTER SHARING IN AN EXTENDED PROCESSOR ARCHITECTURE Mar 12, 2012 Abandoned
Array ( [id] => 8279979 [patent_doc_number] => 20120173848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'PIPELINE FLUSH FOR PROCESSOR THAT MAY EXECUTE INSTRUCTIONS OUT OF ORDER' [patent_app_type] => utility [patent_app_number] => 13/340679 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6509 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13340679 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/340679
PIPELINE FLUSH FOR PROCESSOR THAT MAY EXECUTE INSTRUCTIONS OUT OF ORDER Dec 29, 2011 Abandoned
Array ( [id] => 9213906 [patent_doc_number] => 20140013083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'CACHE COPROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 13/994390 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 19143 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13994390 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/994390
CACHE COPROCESSING UNIT Dec 29, 2011 Abandoned
Array ( [id] => 10249937 [patent_doc_number] => 20150134932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'STRUCTURE ACCESS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/977152 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14203 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977152 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977152
STRUCTURE ACCESS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS Dec 29, 2011 Abandoned
Array ( [id] => 9599102 [patent_doc_number] => 20140195783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'DOT PRODUCT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/977094 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 23881 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977094
DOT PRODUCT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS Dec 28, 2011 Abandoned
Array ( [id] => 9563753 [patent_doc_number] => 20140181466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'PROCESSORS HAVING FULLY-CONNECTED INTERCONNECTS SHARED BY VECTOR CONFLICT INSTRUCTIONS AND PERMUTE INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/977126 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 16873 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977126 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977126
Processors having fully-connected interconnects shared by vector conflict instructions and permute instructions Dec 28, 2011 Issued
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