Search

Jyoti Mehta

Examiner (ID: 2518, Phone: (571)270-3995 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2183, 2182
Total Applications
324
Issued Applications
224
Pending Applications
19
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9044122 [patent_doc_number] => 20130246761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'REGISTER SHARING IN AN EXTENDED PROCESSOR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/418359 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13418359 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/418359
REGISTER SHARING IN AN EXTENDED PROCESSOR ARCHITECTURE Mar 12, 2012 Abandoned
Array ( [id] => 8279979 [patent_doc_number] => 20120173848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'PIPELINE FLUSH FOR PROCESSOR THAT MAY EXECUTE INSTRUCTIONS OUT OF ORDER' [patent_app_type] => utility [patent_app_number] => 13/340679 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6509 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13340679 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/340679
PIPELINE FLUSH FOR PROCESSOR THAT MAY EXECUTE INSTRUCTIONS OUT OF ORDER Dec 29, 2011 Abandoned
Array ( [id] => 10249937 [patent_doc_number] => 20150134932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'STRUCTURE ACCESS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/977152 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14203 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977152 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977152
STRUCTURE ACCESS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS Dec 29, 2011 Abandoned
Array ( [id] => 9213906 [patent_doc_number] => 20140013083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'CACHE COPROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 13/994390 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 19143 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13994390 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/994390
CACHE COPROCESSING UNIT Dec 29, 2011 Abandoned
Array ( [id] => 9563753 [patent_doc_number] => 20140181466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'PROCESSORS HAVING FULLY-CONNECTED INTERCONNECTS SHARED BY VECTOR CONFLICT INSTRUCTIONS AND PERMUTE INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/977126 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 16873 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977126 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977126
Processors having fully-connected interconnects shared by vector conflict instructions and permute instructions Dec 28, 2011 Issued
Array ( [id] => 9599102 [patent_doc_number] => 20140195783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'DOT PRODUCT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/977094 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 23881 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977094
DOT PRODUCT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS Dec 28, 2011 Abandoned
Array ( [id] => 9645027 [patent_doc_number] => 20140223140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING VECTOR PACKED UNARY ENCODING USING MASKS' [patent_app_type] => utility [patent_app_number] => 13/994505 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13994505 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/994505
SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING VECTOR PACKED UNARY ENCODING USING MASKS Dec 22, 2011 Abandoned
Array ( [id] => 9645025 [patent_doc_number] => 20140223138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING CONVERSION OF A MASK REGISTER INTO A VECTOR REGISTER.' [patent_app_type] => utility [patent_app_number] => 13/992235 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 16178 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992235 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992235
SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING CONVERSION OF A MASK REGISTER INTO A VECTOR REGISTER. Dec 22, 2011 Abandoned
Array ( [id] => 9386151 [patent_doc_number] => 20140089634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'APPARATUS AND METHOD FOR DETECTING IDENTICAL ELEMENTS WITHIN A VECTOR REGISTER' [patent_app_type] => utility [patent_app_number] => 13/995490 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15333 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13995490 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/995490
APPARATUS AND METHOD FOR DETECTING IDENTICAL ELEMENTS WITHIN A VECTOR REGISTER Dec 22, 2011 Abandoned
Array ( [id] => 15516761 [patent_doc_number] => 10564966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Packed data operation mask shift processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 13/977171 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 17288 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977171 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977171
Packed data operation mask shift processors, methods, systems, and instructions Dec 21, 2011 Issued
Array ( [id] => 9618208 [patent_doc_number] => 20140208065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'APPARATUS AND METHOD FOR MASK REGISTER EXPAND OPERATION' [patent_app_type] => utility [patent_app_number] => 13/996391 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15018 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13996391 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/996391
APPARATUS AND METHOD FOR MASK REGISTER EXPAND OPERATION Dec 21, 2011 Abandoned
Array ( [id] => 9423829 [patent_doc_number] => 20140108480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'APPARATUS AND METHOD FOR VECTOR COMPUTE AND ACCUMULATE' [patent_app_type] => utility [patent_app_number] => 13/994090 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13994090 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/994090
APPARATUS AND METHOD FOR VECTOR COMPUTE AND ACCUMULATE Dec 21, 2011 Abandoned
Array ( [id] => 8886496 [patent_doc_number] => 20130159680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PARALLELIZING LARGE NUMBER ARITHMETIC' [patent_app_type] => utility [patent_app_number] => 13/330359 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6061 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330359 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/330359
SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PARALLELIZING LARGE NUMBER ARITHMETIC Dec 18, 2011 Abandoned
Array ( [id] => 9847641 [patent_doc_number] => 08949575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency' [patent_app_type] => utility [patent_app_number] => 13/326249 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7633 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13326249 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/326249
Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency Dec 13, 2011 Issued
Array ( [id] => 8868115 [patent_doc_number] => 20130151818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'MICRO ARCHITECTURE FOR INDIRECT ACCESS TO A REGISTER FILE IN A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/323933 [patent_app_country] => US [patent_app_date] => 2011-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13323933 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/323933
MICRO ARCHITECTURE FOR INDIRECT ACCESS TO A REGISTER FILE IN A PROCESSOR Dec 12, 2011 Abandoned
Array ( [id] => 8868113 [patent_doc_number] => 20130151816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'DELAY IDENTIFICATION IN DATA PROCESSING SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/314052 [patent_app_country] => US [patent_app_date] => 2011-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8258 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13314052 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/314052
Prioritizing instructions based on the number of delay cycles Dec 6, 2011 Issued
Array ( [id] => 10170948 [patent_doc_number] => 09201656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Data processing apparatus and method for performing register renaming for certain data processing operations without additional registers' [patent_app_type] => utility [patent_app_number] => 13/309719 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7819 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13309719 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/309719
Data processing apparatus and method for performing register renaming for certain data processing operations without additional registers Dec 1, 2011 Issued
Array ( [id] => 11465652 [patent_doc_number] => 09582284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Performance of processors is improved by limiting number of branch prediction levels' [patent_app_type] => utility [patent_app_number] => 13/308696 [patent_app_country] => US [patent_app_date] => 2011-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5735 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13308696 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/308696
Performance of processors is improved by limiting number of branch prediction levels Nov 30, 2011 Issued
Array ( [id] => 10556151 [patent_doc_number] => 09280352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Lookahead scanning and cracking of microcode instructions in a dispatch queue' [patent_app_type] => utility [patent_app_number] => 13/307969 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6418 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13307969 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307969
Lookahead scanning and cracking of microcode instructions in a dispatch queue Nov 29, 2011 Issued
Array ( [id] => 8843295 [patent_doc_number] => 20130138923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'MULTITHREADED DATA MERGING FOR MULTI-CORE PROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 13/307881 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6496 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13307881 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307881
MULTITHREADED DATA MERGING FOR MULTI-CORE PROCESSING UNIT Nov 29, 2011 Abandoned
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