
Jyoti Mehta
Examiner (ID: 9002, Phone: (571)270-3995 , Office: P/2182 )
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2183, 2182 |
| Total Applications | 338 |
| Issued Applications | 235 |
| Pending Applications | 22 |
| Abandoned Applications | 86 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8735169
[patent_doc_number] => 20130080738
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-28
[patent_title] => 'PROCESSOR CONFIGURED TO PERFORM TRANSACTIONAL MEMORY OPERATIONS'
[patent_app_type] => utility
[patent_app_number] => 13/241775
[patent_app_country] => US
[patent_app_date] => 2011-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7802
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13241775
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/241775 | PROCESSOR CONFIGURED TO PERFORM TRANSACTIONAL MEMORY OPERATIONS | Sep 22, 2011 | Abandoned |
Array
(
[id] => 8038621
[patent_doc_number] => 20120069029
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-22
[patent_title] => 'INTER-PROCESSOR COMMUNICATION TECHNIQUES IN A MULTIPLE-PROCESSOR COMPUTING PLATFORM'
[patent_app_type] => utility
[patent_app_number] => 13/235236
[patent_app_country] => US
[patent_app_date] => 2011-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 29937
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0069/20120069029.pdf
[firstpage_image] =>[orig_patent_app_number] => 13235236
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/235236 | Inter-processor communication techniques in a multiple-processor computing platform | Sep 15, 2011 | Issued |
Array
(
[id] => 10854145
[patent_doc_number] => 08880855
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-04
[patent_title] => 'Dual register data path architecture with registers in a data file divided into groups and sub-groups'
[patent_app_type] => utility
[patent_app_number] => 13/233025
[patent_app_country] => US
[patent_app_date] => 2011-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6909
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 600
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13233025
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/233025 | Dual register data path architecture with registers in a data file divided into groups and sub-groups | Sep 14, 2011 | Issued |
Array
(
[id] => 11390971
[patent_doc_number] => 09552206
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-24
[patent_title] => 'Integrated circuit with control node circuitry and processing circuitry'
[patent_app_type] => utility
[patent_app_number] => 13/232774
[patent_app_country] => US
[patent_app_date] => 2011-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 323
[patent_figures_cnt] => 397
[patent_no_of_words] => 213438
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13232774
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/232774 | Integrated circuit with control node circuitry and processing circuitry | Sep 13, 2011 | Issued |
Array
(
[id] => 8201781
[patent_doc_number] => 20120124351
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-17
[patent_title] => 'APPARATUS AND METHOD FOR DYNAMICALLY DETERMINING EXECUTION MODE OF RECONFIGURABLE ARRAY'
[patent_app_type] => utility
[patent_app_number] => 13/217952
[patent_app_country] => US
[patent_app_date] => 2011-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5942
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20120124351.pdf
[firstpage_image] =>[orig_patent_app_number] => 13217952
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/217952 | Apparatus and method for dynamically determining execution mode of reconfigurable array | Aug 24, 2011 | Issued |
Array
(
[id] => 7792912
[patent_doc_number] => 20120054468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-01
[patent_title] => 'PROCESSOR, APPARATUS, AND METHOD FOR MEMORY MANAGEMENT'
[patent_app_type] => utility
[patent_app_number] => 13/216852
[patent_app_country] => US
[patent_app_date] => 2011-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5421
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20120054468.pdf
[firstpage_image] =>[orig_patent_app_number] => 13216852
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/216852 | PROCESSOR, APPARATUS, AND METHOD FOR MEMORY MANAGEMENT | Aug 23, 2011 | Abandoned |
Array
(
[id] => 7785766
[patent_doc_number] => 20120047322
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-23
[patent_title] => 'Method and System of Using One-Time Programmable Memory as Multi-Time Programmable in Code Memory of Processors'
[patent_app_type] => utility
[patent_app_number] => 13/214183
[patent_app_country] => US
[patent_app_date] => 2011-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6318
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0047/20120047322.pdf
[firstpage_image] =>[orig_patent_app_number] => 13214183
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/214183 | Method and System of Using One-Time Programmable Memory as Multi-Time Programmable in Code Memory of Processors | Aug 19, 2011 | Abandoned |
Array
(
[id] => 8661262
[patent_doc_number] => 20130042091
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-14
[patent_title] => 'BIT Splitting Instruction'
[patent_app_type] => utility
[patent_app_number] => 13/208401
[patent_app_country] => US
[patent_app_date] => 2011-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5503
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13208401
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/208401 | BIT Splitting Instruction | Aug 11, 2011 | Abandoned |
Array
(
[id] => 12088248
[patent_doc_number] => 09841978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-12-12
[patent_title] => 'Processor with a program counter increment based on decoding of predecode bits'
[patent_app_type] => utility
[patent_app_number] => 13/137134
[patent_app_country] => US
[patent_app_date] => 2011-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 9416
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13137134
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/137134 | Processor with a program counter increment based on decoding of predecode bits | Jul 21, 2011 | Issued |
Array
(
[id] => 8619364
[patent_doc_number] => 20130024676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-24
[patent_title] => 'Control flow integrity'
[patent_app_type] => utility
[patent_app_number] => 13/136024
[patent_app_country] => US
[patent_app_date] => 2011-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 14877
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13136024
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/136024 | Control flow integrity | Jul 18, 2011 | Abandoned |
Array
(
[id] => 8267335
[patent_doc_number] => 20120166762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-28
[patent_title] => 'COMPUTING APPARATUS AND METHOD BASED ON A RECONFIGURABLE SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURE'
[patent_app_type] => utility
[patent_app_number] => 13/179367
[patent_app_country] => US
[patent_app_date] => 2011-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4977
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13179367
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/179367 | COMPUTING APPARATUS AND METHOD BASED ON A RECONFIGURABLE SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURE | Jul 7, 2011 | Abandoned |
Array
(
[id] => 7819856
[patent_doc_number] => 20120066476
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-15
[patent_title] => 'MICRO-OPERATION PROCESSING SYSTEM AND DATA WRITING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/177801
[patent_app_country] => US
[patent_app_date] => 2011-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6739
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0066/20120066476.pdf
[firstpage_image] =>[orig_patent_app_number] => 13177801
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/177801 | MICRO-OPERATION PROCESSING SYSTEM AND DATA WRITING METHOD THEREOF | Jul 6, 2011 | Abandoned |
Array
(
[id] => 11830785
[patent_doc_number] => 09727528
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-08
[patent_title] => 'Reconfigurable processor with routing node frequency based on the number of routing nodes'
[patent_app_type] => utility
[patent_app_number] => 13/178062
[patent_app_country] => US
[patent_app_date] => 2011-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5099
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13178062
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/178062 | Reconfigurable processor with routing node frequency based on the number of routing nodes | Jul 6, 2011 | Issued |
Array
(
[id] => 8608587
[patent_doc_number] => 20130013899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-10
[patent_title] => 'Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions'
[patent_app_type] => utility
[patent_app_number] => 13/176833
[patent_app_country] => US
[patent_app_date] => 2011-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9316
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13176833
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/176833 | Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions | Jul 5, 2011 | Abandoned |
Array
(
[id] => 8608537
[patent_doc_number] => 20130013849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-10
[patent_title] => 'Programmable Patch Architecture for ROM'
[patent_app_type] => utility
[patent_app_number] => 13/177328
[patent_app_country] => US
[patent_app_date] => 2011-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4345
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13177328
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/177328 | Programmable Patch Architecture for ROM | Jul 5, 2011 | Abandoned |
Array
(
[id] => 8608583
[patent_doc_number] => 20130013895
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-10
[patent_title] => 'BYTE-ORIENTED MICROCONTROLLER HAVING WIDER PROGRAM MEMORY BUS SUPPORTING MACRO INSTRUCTION EXECUTION, ACCESSING RETURN ADDRESS IN ONE CLOCK CYCLE, STORAGE ACCESSING OPERATION VIA POINTER COMBINATION, AND INCREASED POINTER ADJUSTMENT AMOUNT'
[patent_app_type] => utility
[patent_app_number] => 13/176760
[patent_app_country] => US
[patent_app_date] => 2011-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5990
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13176760
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/176760 | BYTE-ORIENTED MICROCONTROLLER HAVING WIDER PROGRAM MEMORY BUS SUPPORTING MACRO INSTRUCTION EXECUTION, ACCESSING RETURN ADDRESS IN ONE CLOCK CYCLE, STORAGE ACCESSING OPERATION VIA POINTER COMBINATION, AND INCREASED POINTER ADJUSTMENT AMOUNT | Jul 5, 2011 | Abandoned |
Array
(
[id] => 11345190
[patent_doc_number] => 09529596
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-12-27
[patent_title] => 'Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bits'
[patent_app_type] => utility
[patent_app_number] => 13/175619
[patent_app_country] => US
[patent_app_date] => 2011-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8240
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13175619
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/175619 | Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bits | Jun 30, 2011 | Issued |
Array
(
[id] => 7694974
[patent_doc_number] => 20110231616
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-22
[patent_title] => 'DATA PROCESSING METHOD AND SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 13/118360
[patent_app_country] => US
[patent_app_date] => 2011-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 14777
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20110231616.pdf
[firstpage_image] =>[orig_patent_app_number] => 13118360
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/118360 | DATA PROCESSING METHOD AND SYSTEM | May 26, 2011 | Abandoned |
Array
(
[id] => 6093993
[patent_doc_number] => 20110219219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-08
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND REGISTER ADDRESS CONTROLLER'
[patent_app_type] => utility
[patent_app_number] => 13/110664
[patent_app_country] => US
[patent_app_date] => 2011-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3747
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0219/20110219219.pdf
[firstpage_image] =>[orig_patent_app_number] => 13110664
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/110664 | SEMICONDUCTOR INTEGRATED CIRCUIT AND REGISTER ADDRESS CONTROLLER | May 17, 2011 | Abandoned |
Array
(
[id] => 8491414
[patent_doc_number] => 20120290821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-15
[patent_title] => 'LOW-LATENCY BRANCH TARGET CACHE'
[patent_app_type] => utility
[patent_app_number] => 13/105606
[patent_app_country] => US
[patent_app_date] => 2011-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 14587
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13105606
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/105606 | LOW-LATENCY BRANCH TARGET CACHE | May 10, 2011 | Abandoned |