Search

Jyoti Mehta

Examiner (ID: 2518, Phone: (571)270-3995 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2183, 2182
Total Applications
324
Issued Applications
224
Pending Applications
19
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17515699 [patent_doc_number] => 11294850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => System, apparatus and method for increasing bandwidth of edge-located agents of an integrated circuit [patent_app_type] => utility [patent_app_number] => 16/369220 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7073 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369220
System, apparatus and method for increasing bandwidth of edge-located agents of an integrated circuit Mar 28, 2019 Issued
Array ( [id] => 17423059 [patent_doc_number] => 11256513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Indirect control flow instructions and inhibiting data value speculation [patent_app_type] => utility [patent_app_number] => 17/043921 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 11405 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17043921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/043921
Indirect control flow instructions and inhibiting data value speculation Mar 13, 2019 Issued
Array ( [id] => 17164806 [patent_doc_number] => 11150902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Processor pipeline management during cache misses using next-best ticket identifier for sleep and wakeup [patent_app_type] => utility [patent_app_number] => 16/272262 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5592 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272262 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/272262
Processor pipeline management during cache misses using next-best ticket identifier for sleep and wakeup Feb 10, 2019 Issued
Array ( [id] => 16745082 [patent_doc_number] => 10970072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Systems and methods to transpose vectors on-the-fly while loading from memory [patent_app_type] => utility [patent_app_number] => 16/231050 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 20468 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231050 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/231050
Systems and methods to transpose vectors on-the-fly while loading from memory Dec 20, 2018 Issued
Array ( [id] => 17364910 [patent_doc_number] => 11231931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-25 [patent_title] => Mechanism for mitigating information leak via cache side channels during speculative execution [patent_app_type] => utility [patent_app_number] => 16/228187 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228187
Mechanism for mitigating information leak via cache side channels during speculative execution Dec 19, 2018 Issued
Array ( [id] => 16095319 [patent_doc_number] => 20200201646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => MULTIPLE STREAMS EXECUTION FOR BRANCH PREDICATION IN A MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 16/226729 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226729 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226729
Multiple streams execution for hard-to-predict branches in a microprocessor Dec 19, 2018 Issued
Array ( [id] => 17016994 [patent_doc_number] => 11086633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engine [patent_app_type] => utility [patent_app_number] => 16/226508 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12784 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226508 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226508
Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engine Dec 18, 2018 Issued
Array ( [id] => 14188931 [patent_doc_number] => 20190114171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => SELECTING PROCESSING BASED ON EXPECTED VALUE OF SELECTED CHARACTER [patent_app_type] => utility [patent_app_number] => 16/212952 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16212952 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/212952
Selecting processing based on expected value of selected character Dec 6, 2018 Issued
Array ( [id] => 14669093 [patent_doc_number] => 10372447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Selecting processing based on expected value of selected character [patent_app_type] => utility [patent_app_number] => 16/212919 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 21260 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16212919 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/212919
Selecting processing based on expected value of selected character Dec 6, 2018 Issued
Array ( [id] => 16017785 [patent_doc_number] => 20200183736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => Coprocessor Memory Ordering Table [patent_app_type] => utility [patent_app_number] => 16/210231 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16210231 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/210231
Coprocessor memory ordering table Dec 4, 2018 Issued
Array ( [id] => 14539037 [patent_doc_number] => 20190205140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => SPECULATION BARRIER INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/208701 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208701 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/208701
Speculation barrier instruction Dec 3, 2018 Issued
Array ( [id] => 15997851 [patent_doc_number] => 20200174796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => FASTER SPARSE FLUSH RECOVERY [patent_app_type] => utility [patent_app_number] => 16/207548 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16207548 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/207548
Faster sparse flush recovery by creating groups that are marked based on an instruction type Dec 2, 2018 Issued
Array ( [id] => 15935803 [patent_doc_number] => 20200159535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => REGISTER DEALLOCATION IN A PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/194456 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194456 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194456
REGISTER DEALLOCATION IN A PROCESSING SYSTEM Nov 18, 2018 Abandoned
Array ( [id] => 17238286 [patent_doc_number] => 11182165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Skip-over offset branch prediction [patent_app_type] => utility [patent_app_number] => 16/194452 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9245 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194452 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194452
Skip-over offset branch prediction Nov 18, 2018 Issued
Array ( [id] => 14443527 [patent_doc_number] => 20190179637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => MULTIVALUE REDUCTIONS USING SERIAL INITIAL REDUCTIONS IN MULTIPLE REGISTER SPACES AND PARALLEL SUBSEQUENT REDUCTIONS IN A SINGLE REGISTER SPACE [patent_app_type] => utility [patent_app_number] => 16/194217 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194217 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194217
Multivalue reductions using serial initial reductions in multiple register spaces and parallel subsequent reductions in a single register space Nov 15, 2018 Issued
Array ( [id] => 17572828 [patent_doc_number] => 11321096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Hardware unit for performing matrix multiplication with clock gating [patent_app_type] => utility [patent_app_number] => 16/180181 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13499 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16180181 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/180181
Hardware unit for performing matrix multiplication with clock gating Nov 4, 2018 Issued
Array ( [id] => 15714793 [patent_doc_number] => 20200104163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => PROVIDING PREDICTIVE INSTRUCTION DISPATCH THROTTLING TO PREVENT RESOURCE OVERFLOWS IN OUT-OF-ORDER PROCESSOR (OOP)-BASED DEVICES [patent_app_type] => utility [patent_app_number] => 16/143883 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143883 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143883
Providing predictive instruction dispatch throttling to prevent resource overflows in out-of-order processor (OOP)-based devices Sep 26, 2018 Issued
Array ( [id] => 14161855 [patent_doc_number] => 20190108030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK [patent_app_type] => utility [patent_app_number] => 16/145160 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145160
SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK Sep 26, 2018 Abandoned
Array ( [id] => 13845257 [patent_doc_number] => 20190026113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => FAST MULTI-WIDTH INSTRUCTION ISSUE IN PARALLEL SLICE PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/141285 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/141285
Fast multi-width instruction issue in parallel slice processor Sep 24, 2018 Issued
Array ( [id] => 16446799 [patent_doc_number] => 10838728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Parallel slice processor shadowing states of hardware threads across execution slices [patent_app_type] => utility [patent_app_number] => 16/139685 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8831 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139685 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139685
Parallel slice processor shadowing states of hardware threads across execution slices Sep 23, 2018 Issued
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