Search

Jyoti Mehta

Examiner (ID: 14098, Phone: (571)270-3995 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183
Total Applications
312
Issued Applications
218
Pending Applications
12
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12756268 [patent_doc_number] => 20180143923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => Providing State Storage in a Processor for System Management Mode [patent_app_type] => utility [patent_app_number] => 15/873089 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873089 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/873089
Providing State Storage in a Processor for System Management Mode Jan 16, 2018 Abandoned
Array ( [id] => 17408872 [patent_doc_number] => 11249754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Apparatus and method for vector horizontal add of signed/unsigned words and doublewords [patent_app_type] => utility [patent_app_number] => 15/850131 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 13147 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850131 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850131
Apparatus and method for vector horizontal add of signed/unsigned words and doublewords Dec 20, 2017 Issued
Array ( [id] => 12869719 [patent_doc_number] => 20180181748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => HARDWARE MONITOR OF A PROCESSING UNIT STACK STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/847827 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847827 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/847827
Stack overflow protection by monitoring addresses of a stack of multi-bit protection codes Dec 18, 2017 Issued
Array ( [id] => 13240749 [patent_doc_number] => 10133573 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-20 [patent_title] => Multivalue reductions using serial initial reductions in multiple register spaces and parallel subsequent reductions in a single register space [patent_app_type] => utility [patent_app_number] => 15/839637 [patent_app_country] => US [patent_app_date] => 2017-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5176 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/839637
Multivalue reductions using serial initial reductions in multiple register spaces and parallel subsequent reductions in a single register space Dec 11, 2017 Issued
Array ( [id] => 14457513 [patent_doc_number] => 10324717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Selecting processing based on expected value of selected character [patent_app_type] => utility [patent_app_number] => 15/825802 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 21275 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825802 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825802
Selecting processing based on expected value of selected character Nov 28, 2017 Issued
Array ( [id] => 12571041 [patent_doc_number] => 10019265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Selectively blocking branch prediction for a predetermined number of instructions [patent_app_type] => utility [patent_app_number] => 15/818810 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7952 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818810 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/818810
Selectively blocking branch prediction for a predetermined number of instructions Nov 20, 2017 Issued
Array ( [id] => 13003847 [patent_doc_number] => 10025592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Selectively blocking branch prediction for a predetermined number of instructions [patent_app_type] => utility [patent_app_number] => 15/818808 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7886 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818808 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/818808
Selectively blocking branch prediction for a predetermined number of instructions Nov 20, 2017 Issued
Array ( [id] => 13511899 [patent_doc_number] => 20180307492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => SYSTEM AND METHOD OF REDUCING PROCESSOR PIPELINE STALL CAUSED BY FULL LOAD QUEUE [patent_app_type] => utility [patent_app_number] => 15/810835 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810835 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810835
System and method of reducing processor pipeline stall caused by full load queue Nov 12, 2017 Issued
Array ( [id] => 14235089 [patent_doc_number] => 20190129717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => EFFICIENT MANAGEMENT OF SCRATCH REGISTERS [patent_app_type] => utility [patent_app_number] => 15/800321 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800321 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800321
Suppress unnecessary mapping for scratch register Oct 31, 2017 Issued
Array ( [id] => 13120319 [patent_doc_number] => 10078513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-18 [patent_title] => Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements [patent_app_type] => utility [patent_app_number] => 15/799033 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 15569 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799033 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799033
Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements Oct 30, 2017 Issued
Array ( [id] => 13467131 [patent_doc_number] => 20180285108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => BRANCH PREDICTION USING A PERCEPTRON-BASED BRANCH PREDICTION TECHNIQUE [patent_app_type] => utility [patent_app_number] => 15/794436 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794436 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/794436
BRANCH PREDICTION USING A PERCEPTRON-BASED BRANCH PREDICTION TECHNIQUE Oct 25, 2017 Abandoned
Array ( [id] => 16607900 [patent_doc_number] => 10908903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Efficiency for coordinated start interpretive execution exit for a multithreaded processor [patent_app_type] => utility [patent_app_number] => 15/717279 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8652 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717279 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/717279
Efficiency for coordinated start interpretive execution exit for a multithreaded processor Sep 26, 2017 Issued
Array ( [id] => 17164809 [patent_doc_number] => 11150905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Efficiency for coordinated start interpretive execution exit for a multithreaded processor [patent_app_type] => utility [patent_app_number] => 15/717487 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8666 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717487 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/717487
Efficiency for coordinated start interpretive execution exit for a multithreaded processor Sep 26, 2017 Issued
Array ( [id] => 12688117 [patent_doc_number] => 20180121205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => OUT-OF-ORDER PROCESSOR THAT AVOIDS DEADLOCK IN PROCESSING QUEUES BY DESIGNATING A MOST FAVORED INSTRUCTION [patent_app_type] => utility [patent_app_number] => 15/693387 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693387 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693387
Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction Aug 30, 2017 Issued
Array ( [id] => 13992075 [patent_doc_number] => 20190065195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => INLINE DATA INSPECTION FOR WORKLOAD SIMPLIFICATION [patent_app_type] => utility [patent_app_number] => 15/693345 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693345 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693345
Inline data inspection for workload simplification Aug 30, 2017 Issued
Array ( [id] => 13993613 [patent_doc_number] => 20190065964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => METHOD AND APPARATUS FOR LOAD VALUE PREDICTION [patent_app_type] => utility [patent_app_number] => 15/691741 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691741 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691741
METHOD AND APPARATUS FOR LOAD VALUE PREDICTION Aug 29, 2017 Abandoned
Array ( [id] => 12712996 [patent_doc_number] => 20180129498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 15/690560 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690560 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690560
MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS Aug 29, 2017 Abandoned
Array ( [id] => 12713005 [patent_doc_number] => 20180129501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 15/690536 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690536
MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS Aug 29, 2017 Abandoned
Array ( [id] => 13991805 [patent_doc_number] => 20190065060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => CACHING INSTRUCTION BLOCK HEADER DATA IN BLOCK ARCHITECTURE PROCESSOR-BASED SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/688191 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15688191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/688191
CACHING INSTRUCTION BLOCK HEADER DATA IN BLOCK ARCHITECTURE PROCESSOR-BASED SYSTEMS Aug 27, 2017 Abandoned
Array ( [id] => 12094432 [patent_doc_number] => 20170351525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'Method and Apparatus for Allocating Hardware Acceleration Instruction to Memory Controller' [patent_app_type] => utility [patent_app_number] => 15/687164 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8179 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687164 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687164
Method and Apparatus for Allocating Hardware Acceleration Instruction to Memory Controller Aug 24, 2017 Abandoned
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