Search

Jyoti Mehta

Examiner (ID: 9002, Phone: (571)270-3995 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2183, 2182
Total Applications
338
Issued Applications
235
Pending Applications
22
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12713005 [patent_doc_number] => 20180129501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 15/690536 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690536
MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS Aug 29, 2017 Abandoned
Array ( [id] => 12712996 [patent_doc_number] => 20180129498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 15/690560 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690560 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690560
MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS Aug 29, 2017 Abandoned
Array ( [id] => 13991805 [patent_doc_number] => 20190065060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => CACHING INSTRUCTION BLOCK HEADER DATA IN BLOCK ARCHITECTURE PROCESSOR-BASED SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/688191 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15688191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/688191
CACHING INSTRUCTION BLOCK HEADER DATA IN BLOCK ARCHITECTURE PROCESSOR-BASED SYSTEMS Aug 27, 2017 Abandoned
Array ( [id] => 12094432 [patent_doc_number] => 20170351525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'Method and Apparatus for Allocating Hardware Acceleration Instruction to Memory Controller' [patent_app_type] => utility [patent_app_number] => 15/687164 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8179 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687164 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687164
Method and Apparatus for Allocating Hardware Acceleration Instruction to Memory Controller Aug 24, 2017 Abandoned
Array ( [id] => 16551585 [patent_doc_number] => 10884744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => System and method of loop vectorization by compressing indices and data elements from iterations based on a control mask [patent_app_type] => utility [patent_app_number] => 15/681303 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 13486 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681303 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681303
System and method of loop vectorization by compressing indices and data elements from iterations based on a control mask Aug 17, 2017 Issued
Array ( [id] => 13933431 [patent_doc_number] => 20190050231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => SLAVE PROCESSOR WITHIN A SYSTEM-ON-CHIP [patent_app_type] => utility [patent_app_number] => 15/676453 [patent_app_country] => US [patent_app_date] => 2017-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15676453 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/676453
Slave processor within a system-on-chip Aug 13, 2017 Issued
Array ( [id] => 13721337 [patent_doc_number] => 20170371623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => STOCHASTIC PROCESSING [patent_app_type] => utility [patent_app_number] => 15/676324 [patent_app_country] => US [patent_app_date] => 2017-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15676324 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/676324
Stochastic processing Aug 13, 2017 Issued
Array ( [id] => 11973386 [patent_doc_number] => 20170277540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'Processor with a Program Counter Increment Based on Decoding of Predecode Bits' [patent_app_type] => utility [patent_app_number] => 15/612247 [patent_app_country] => US [patent_app_date] => 2017-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9447 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15612247 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/612247
Processor with a program counter increment based on decoding of predecode bits Jun 1, 2017 Issued
Array ( [id] => 12120942 [patent_doc_number] => 20180004528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'ARITHMETIC PROCESSING DEVICE AND CONTROL METHOD OF ARITHMETIC PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 15/601086 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7939 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601086 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/601086
Arithmetic processing device for predicting loop processing May 21, 2017 Issued
Array ( [id] => 14952671 [patent_doc_number] => 10437600 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-08 [patent_title] => Memory hierarchy to transfer vector data for operators of a directed acyclic graph [patent_app_type] => utility [patent_app_number] => 15/593463 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9429 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593463 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/593463
Memory hierarchy to transfer vector data for operators of a directed acyclic graph May 11, 2017 Issued
Array ( [id] => 13556633 [patent_doc_number] => 20180329864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => IMAGE PROCESSOR WITH CONFIGURABLE NUMBER OF ACTIVE CORES AND SUPPORTING INTERNAL NETWORK [patent_app_type] => utility [patent_app_number] => 15/594502 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15594502 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/594502
Image processor with configurable number of active cores and supporting internal network May 11, 2017 Issued
Array ( [id] => 11938654 [patent_doc_number] => 20170242803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'SYSTEMS AND METHODS FOR PERFORMING INSTRUCTION FETCHES BASED ON PRIVILEGE STATES AND CODE MEMORY REGIONS' [patent_app_type] => utility [patent_app_number] => 15/585910 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12427 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/585910
Processing systems and methods for transitioning between privilege states based on an address of a next instruction to be fetched May 2, 2017 Issued
Array ( [id] => 14523321 [patent_doc_number] => 10338921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Asynchronous instruction execution apparatus with execution modules invoking external calculation resources [patent_app_type] => utility [patent_app_number] => 15/482550 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8526 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482550 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/482550
Asynchronous instruction execution apparatus with execution modules invoking external calculation resources Apr 6, 2017 Issued
Array ( [id] => 13467129 [patent_doc_number] => 20180285107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => BRANCH PREDICTION USING A PERCEPTRON-BASED BRANCH PREDICTION TECHNIQUE [patent_app_type] => utility [patent_app_number] => 15/475192 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475192 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475192
BRANCH PREDICTION USING A PERCEPTRON-BASED BRANCH PREDICTION TECHNIQUE Mar 30, 2017 Abandoned
Array ( [id] => 11731336 [patent_doc_number] => 20170192779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'SCHEDULING EXECUTION OF INSTRUCTIONS ON A PROCESSOR HAVING MULTIPLE HARDWARE THREADS WITH DIFFERENT EXECUTION RESOURCES' [patent_app_type] => utility [patent_app_number] => 15/467073 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3204 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467073 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/467073
Scheduling execution of instructions on a processor having multiple hardware threads with different execution resources Mar 22, 2017 Issued
Array ( [id] => 11752253 [patent_doc_number] => 09710265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-18 [patent_title] => 'Neural network compute tile' [patent_app_type] => utility [patent_app_number] => 15/462180 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10014 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462180 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/462180
Neural network compute tile Mar 16, 2017 Issued
Array ( [id] => 16338114 [patent_doc_number] => 10789069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Dynamically selecting version of instruction to be executed [patent_app_type] => utility [patent_app_number] => 15/449183 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 21080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/449183
Dynamically selecting version of instruction to be executed Mar 2, 2017 Issued
Array ( [id] => 14457511 [patent_doc_number] => 10324716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Selecting processing based on expected value of selected character [patent_app_type] => utility [patent_app_number] => 15/449219 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 21255 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/449219
Selecting processing based on expected value of selected character Mar 2, 2017 Issued
Array ( [id] => 12986038 [patent_doc_number] => 20170344373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => DISTANCE-BASED BRANCH PREDICTION AND DETECTION [patent_app_type] => utility [patent_app_number] => 15/440383 [patent_app_country] => US [patent_app_date] => 2017-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15440383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/440383
DISTANCE-BASED BRANCH PREDICTION AND DETECTION Feb 22, 2017 Abandoned
Array ( [id] => 14061777 [patent_doc_number] => 10235181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Out-of-order processor and method for back to back instruction issue [patent_app_type] => utility [patent_app_number] => 15/424682 [patent_app_country] => US [patent_app_date] => 2017-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3771 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15424682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/424682
Out-of-order processor and method for back to back instruction issue Feb 2, 2017 Issued
Menu