Search

Jyoti Mehta

Examiner (ID: 14098, Phone: (571)270-3995 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183
Total Applications
312
Issued Applications
218
Pending Applications
12
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11931551 [patent_doc_number] => 09798549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-24 [patent_title] => 'Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction' [patent_app_type] => utility [patent_app_number] => 15/338691 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4431 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338691 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338691
Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction Oct 30, 2016 Issued
Array ( [id] => 13767277 [patent_doc_number] => 10175980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Neural network compute tile [patent_app_type] => utility [patent_app_number] => 15/335769 [patent_app_country] => US [patent_app_date] => 2016-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15335769 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/335769
Neural network compute tile Oct 26, 2016 Issued
Array ( [id] => 13226529 [patent_doc_number] => 10127040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Processor and method for executing memory access and computing instructions for host matrix operations [patent_app_type] => utility [patent_app_number] => 15/279217 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5847 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279217 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/279217
Processor and method for executing memory access and computing instructions for host matrix operations Sep 27, 2016 Issued
Array ( [id] => 15952737 [patent_doc_number] => 10664276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Remote command invocation using a register for storing a command and an attention bit indicating command has been issued [patent_app_type] => utility [patent_app_number] => 15/278265 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5160 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15278265 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/278265
Remote command invocation using a register for storing a command and an attention bit indicating command has been issued Sep 27, 2016 Issued
Array ( [id] => 15284665 [patent_doc_number] => 10514997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Multi-producer single consumer lock-free queues with producer reference counting [patent_app_type] => utility [patent_app_number] => 15/277683 [patent_app_country] => US [patent_app_date] => 2016-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277683 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/277683
Multi-producer single consumer lock-free queues with producer reference counting Sep 26, 2016 Issued
Array ( [id] => 12591351 [patent_doc_number] => 20180088946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR MIXING VECTOR OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/277963 [patent_app_country] => US [patent_app_date] => 2016-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/277963
APPARATUSES, METHODS, AND SYSTEMS FOR MIXING VECTOR OPERATIONS Sep 26, 2016 Abandoned
Array ( [id] => 15731117 [patent_doc_number] => 10613987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Operand cache coherence for SIMD processor supporting predication [patent_app_type] => utility [patent_app_number] => 15/274098 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15274098 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/274098
Operand cache coherence for SIMD processor supporting predication Sep 22, 2016 Issued
Array ( [id] => 16446791 [patent_doc_number] => 10838720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Methods and processors having instructions to determine middle, lowest, or highest values of corresponding elements of three vectors [patent_app_type] => utility [patent_app_number] => 15/274849 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 21890 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15274849 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/274849
Methods and processors having instructions to determine middle, lowest, or highest values of corresponding elements of three vectors Sep 22, 2016 Issued
Array ( [id] => 14601031 [patent_doc_number] => 10353708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Strided loading of non-sequential memory locations by skipping memory locations between consecutive loads [patent_app_type] => utility [patent_app_number] => 15/273916 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5547 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273916 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273916
Strided loading of non-sequential memory locations by skipping memory locations between consecutive loads Sep 22, 2016 Issued
Array ( [id] => 13752643 [patent_doc_number] => 10169268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Providing state storage in a processor for system management mode [patent_app_type] => utility [patent_app_number] => 15/270151 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270151 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270151
Providing state storage in a processor for system management mode Sep 19, 2016 Issued
Array ( [id] => 11365991 [patent_doc_number] => 20170003973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'Processor with Instruction Concatenation' [patent_app_type] => utility [patent_app_number] => 15/265184 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5345 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15265184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/265184
Execution of additional instructions prior to a first instruction in an interruptible or non-interruptible manner as specified in an instruction field Sep 13, 2016 Issued
Array ( [id] => 12213961 [patent_doc_number] => 09910770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Microcomputer having processor capable of changing endian based on endian information in memory' [patent_app_type] => utility [patent_app_number] => 15/197078 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4001 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15197078 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/197078
Microcomputer having processor capable of changing endian based on endian information in memory Jun 28, 2016 Issued
Array ( [id] => 16607899 [patent_doc_number] => 10908902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Distance based branch prediction and detection of potential call and potential return instructions [patent_app_type] => utility [patent_app_number] => 15/165395 [patent_app_country] => US [patent_app_date] => 2016-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4714 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15165395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/165395
Distance based branch prediction and detection of potential call and potential return instructions May 25, 2016 Issued
Array ( [id] => 12532206 [patent_doc_number] => 10007590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Identifying and tracking frequently accessed registers in a processor [patent_app_type] => utility [patent_app_number] => 15/098430 [patent_app_country] => US [patent_app_date] => 2016-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7321 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15098430 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/098430
Identifying and tracking frequently accessed registers in a processor Apr 13, 2016 Issued
Array ( [id] => 11326949 [patent_doc_number] => 20160357561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'APPARATUS HAVING PROCESSING PIPELINE WITH FIRST AND SECOND EXECUTION CIRCUITRY, AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/097377 [patent_app_country] => US [patent_app_date] => 2016-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9915 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15097377 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/097377
APPARATUS HAVING PROCESSING PIPELINE WITH FIRST AND SECOND EXECUTION CIRCUITRY, AND METHOD Apr 12, 2016 Abandoned
Array ( [id] => 15886857 [patent_doc_number] => 10649773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Processors supporting atomic writes to multiword memory locations and methods [patent_app_type] => utility [patent_app_number] => 15/092915 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6860 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092915 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/092915
Processors supporting atomic writes to multiword memory locations and methods Apr 6, 2016 Issued
Array ( [id] => 12495222 [patent_doc_number] => 09996359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Fast multi-width instruction issue in parallel slice processor [patent_app_type] => utility [patent_app_number] => 15/093192 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15093192 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/093192
Fast multi-width instruction issue in parallel slice processor Apr 6, 2016 Issued
Array ( [id] => 11989333 [patent_doc_number] => 20170293488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'ROTATIONAL DISPATCH FOR PARALLEL SLICE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/093172 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15093172 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/093172
Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port Apr 6, 2016 Issued
Array ( [id] => 16200617 [patent_doc_number] => 10725780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Convert to zoned format from decimal floating point format [patent_app_type] => utility [patent_app_number] => 15/083362 [patent_app_country] => US [patent_app_date] => 2016-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 17597 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15083362 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/083362
Convert to zoned format from decimal floating point format Mar 28, 2016 Issued
Array ( [id] => 11013190 [patent_doc_number] => 20160210143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT' [patent_app_type] => utility [patent_app_number] => 15/082694 [patent_app_country] => US [patent_app_date] => 2016-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 18062 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15082694 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/082694
Convert to zoned format from decimal floating point format Mar 27, 2016 Issued
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