
Kajli Prince
Examiner (ID: 7158)
| Most Active Art Unit | 2874 |
| Art Unit(s) | 2874 |
| Total Applications | 361 |
| Issued Applications | 303 |
| Pending Applications | 0 |
| Abandoned Applications | 64 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1554691
[patent_doc_number] => 06348731
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-19
[patent_title] => 'Copper interconnections with enhanced electromigration resistance and reduced defect sensitivity and method of forming same'
[patent_app_type] => B1
[patent_app_number] => 09/240950
[patent_app_country] => US
[patent_app_date] => 1999-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 5087
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[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/348/06348731.pdf
[firstpage_image] =>[orig_patent_app_number] => 09240950
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/240950 | Copper interconnections with enhanced electromigration resistance and reduced defect sensitivity and method of forming same | Jan 28, 1999 | Issued |
Array
(
[id] => 1402119
[patent_doc_number] => 06534393
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-18
[patent_title] => 'Method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity'
[patent_app_type] => B1
[patent_app_number] => 09/236487
[patent_app_country] => US
[patent_app_date] => 1999-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3953
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/534/06534393.pdf
[firstpage_image] =>[orig_patent_app_number] => 09236487
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/236487 | Method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity | Jan 24, 1999 | Issued |
Array
(
[id] => 1588926
[patent_doc_number] => 06482734
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-19
[patent_title] => 'Diffusion barrier layer for semiconductor device and fabrication method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/233040
[patent_app_country] => US
[patent_app_date] => 1999-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 2727
[patent_no_of_claims] => 15
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[patent_words_short_claim] => 141
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/482/06482734.pdf
[firstpage_image] =>[orig_patent_app_number] => 09233040
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/233040 | Diffusion barrier layer for semiconductor device and fabrication method thereof | Jan 19, 1999 | Issued |
Array
(
[id] => 4102405
[patent_doc_number] => 06051470
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Dual-gate MOSFET with channel potential engineering'
[patent_app_type] => 1
[patent_app_number] => 9/231651
[patent_app_country] => US
[patent_app_date] => 1999-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2217
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/051/06051470.pdf
[firstpage_image] =>[orig_patent_app_number] => 231651
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/231651 | Dual-gate MOSFET with channel potential engineering | Jan 14, 1999 | Issued |
Array
(
[id] => 4138846
[patent_doc_number] => 06060333
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Method of making a liquid crystal display including a field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 9/228937
[patent_app_country] => US
[patent_app_date] => 1999-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 12396
[patent_no_of_claims] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/060/06060333.pdf
[firstpage_image] =>[orig_patent_app_number] => 228937
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/228937 | Method of making a liquid crystal display including a field effect transistor | Jan 11, 1999 | Issued |
Array
(
[id] => 4259433
[patent_doc_number] => 06258707
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Triple damascence tungsten-copper interconnect structure'
[patent_app_type] => 1
[patent_app_number] => 9/227010
[patent_app_country] => US
[patent_app_date] => 1999-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/258/06258707.pdf
[firstpage_image] =>[orig_patent_app_number] => 227010
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/227010 | Triple damascence tungsten-copper interconnect structure | Jan 6, 1999 | Issued |
Array
(
[id] => 1336462
[patent_doc_number] => 06593230
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/225557
[patent_app_country] => US
[patent_app_date] => 1999-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 5134
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/593/06593230.pdf
[firstpage_image] =>[orig_patent_app_number] => 09225557
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/225557 | Method of manufacturing semiconductor device | Jan 4, 1999 | Issued |
Array
(
[id] => 1450023
[patent_doc_number] => 06455403
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Shallow trench contact structure to solve the problem of schottky diode leakage'
[patent_app_type] => B1
[patent_app_number] => 09/225377
[patent_app_country] => US
[patent_app_date] => 1999-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2088
[patent_no_of_claims] => 18
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/455/06455403.pdf
[firstpage_image] =>[orig_patent_app_number] => 09225377
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/225377 | Shallow trench contact structure to solve the problem of schottky diode leakage | Jan 3, 1999 | Issued |
Array
(
[id] => 1542782
[patent_doc_number] => 06372650
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Method of cleaning substrate and method of manufacturing semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/220690
[patent_app_country] => US
[patent_app_date] => 1998-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3318
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/372/06372650.pdf
[firstpage_image] =>[orig_patent_app_number] => 09220690
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/220690 | Method of cleaning substrate and method of manufacturing semiconductor device | Dec 27, 1998 | Issued |
Array
(
[id] => 6934496
[patent_doc_number] => 20010055840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-12-27
[patent_title] => 'METHOD FOR FABRICATING NARROW METAL INTERCONNECTS IN AN INTEGRATED CIRCUIT USING HEAT AND PRESSURE TO EXTRUDE A METAL LAYER INTO A LEAD TRENCH AND VIA/CONTACT'
[patent_app_type] => new
[patent_app_number] => 09/216220
[patent_app_country] => US
[patent_app_date] => 1998-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5439
[patent_no_of_claims] => 16
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0055/20010055840.pdf
[firstpage_image] =>[orig_patent_app_number] => 09216220
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/216220 | METHOD FOR FABRICATING NARROW METAL INTERCONNECTS IN AN INTEGRATED CIRCUIT USING HEAT AND PRESSURE TO EXTRUDE A METAL LAYER INTO A LEAD TRENCH AND VIA/CONTACT | Dec 17, 1998 | Abandoned |
Array
(
[id] => 4406302
[patent_doc_number] => 06171953
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Processes for making electronic devices with rubidum barrier film'
[patent_app_type] => 1
[patent_app_number] => 9/215128
[patent_app_country] => US
[patent_app_date] => 1998-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 8278
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[pdf_file] => patents/06/171/06171953.pdf
[firstpage_image] =>[orig_patent_app_number] => 215128
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/215128 | Processes for making electronic devices with rubidum barrier film | Dec 17, 1998 | Issued |
Array
(
[id] => 4250543
[patent_doc_number] => 06207559
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Method of making a semiconductor device for attachment to a semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 9/196566
[patent_app_country] => US
[patent_app_date] => 1998-11-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/207/06207559.pdf
[firstpage_image] =>[orig_patent_app_number] => 196566
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/196566 | Method of making a semiconductor device for attachment to a semiconductor substrate | Nov 19, 1998 | Issued |
Array
(
[id] => 4125309
[patent_doc_number] => 06127256
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Semiconductor device and method of manufacturing the same'
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[patent_app_date] => 1998-11-10
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[pdf_file] => patents/06/127/06127256.pdf
[firstpage_image] =>[orig_patent_app_number] => 189640
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/189640 | Semiconductor device and method of manufacturing the same | Nov 9, 1998 | Issued |
Array
(
[id] => 4094690
[patent_doc_number] => 06096608
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench'
[patent_app_type] => 1
[patent_app_number] => 9/186216
[patent_app_country] => US
[patent_app_date] => 1998-11-03
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/096/06096608.pdf
[firstpage_image] =>[orig_patent_app_number] => 186216
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/186216 | Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench | Nov 2, 1998 | Issued |
Array
(
[id] => 4107875
[patent_doc_number] => 06057225
[patent_country] => US
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[patent_issue_date] => 2000-05-02
[patent_title] => 'Semiconductor integrated circuit device having fundamental cells and method of manufacturing the semiconductor integrated circuit device using the fundamental cells'
[patent_app_type] => 1
[patent_app_number] => 9/184970
[patent_app_country] => US
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[pdf_file] => patents/06/057/06057225.pdf
[firstpage_image] =>[orig_patent_app_number] => 184970
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/184970 | Semiconductor integrated circuit device having fundamental cells and method of manufacturing the semiconductor integrated circuit device using the fundamental cells | Nov 2, 1998 | Issued |
Array
(
[id] => 724444
[patent_doc_number] => 07045435
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-05-16
[patent_title] => 'Shallow trench isolation method for a semiconductor wafer'
[patent_app_type] => utility
[patent_app_number] => 09/187197
[patent_app_country] => US
[patent_app_date] => 1998-11-03
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/045/07045435.pdf
[firstpage_image] =>[orig_patent_app_number] => 09187197
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/187197 | Shallow trench isolation method for a semiconductor wafer | Nov 2, 1998 | Issued |
Array
(
[id] => 4302933
[patent_doc_number] => 06251802
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-26
[patent_title] => 'Methods of forming carbon-containing layers'
[patent_app_type] => 1
[patent_app_number] => 9/175051
[patent_app_country] => US
[patent_app_date] => 1998-10-19
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[pdf_file] => patents/06/251/06251802.pdf
[firstpage_image] =>[orig_patent_app_number] => 175051
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/175051 | Methods of forming carbon-containing layers | Oct 18, 1998 | Issued |
Array
(
[id] => 4344621
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[patent_issue_date] => 2001-09-04
[patent_title] => 'Method of forming a contact using a sacrificial spacer'
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[firstpage_image] =>[orig_patent_app_number] => 174300
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/174300 | Method of forming a contact using a sacrificial spacer | Oct 15, 1998 | Issued |
Array
(
[id] => 6973609
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[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-06-14
[patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING REFRACTORY METAL SILICIDE FILM'
[patent_app_type] => new-utility
[patent_app_number] => 09/172800
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/172800 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING REFRACTORY METAL SILICIDE FILM | Oct 13, 1998 | Abandoned |
Array
(
[id] => 4326936
[patent_doc_number] => 06319794
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Structure and method for producing low leakage isolation devices'
[patent_app_type] => 1
[patent_app_number] => 9/172697
[patent_app_country] => US
[patent_app_date] => 1998-10-14
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/319/06319794.pdf
[firstpage_image] =>[orig_patent_app_number] => 172697
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/172697 | Structure and method for producing low leakage isolation devices | Oct 13, 1998 | Issued |