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Kajli Prince

Examiner (ID: 7158)

Most Active Art Unit
2874
Art Unit(s)
2874
Total Applications
361
Issued Applications
303
Pending Applications
0
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4070077 [patent_doc_number] => 05933750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method of fabricating a semiconductor device with a thinned substrate' [patent_app_type] => 1 [patent_app_number] => 9/054561 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1678 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933750.pdf [firstpage_image] =>[orig_patent_app_number] => 054561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/054561
Method of fabricating a semiconductor device with a thinned substrate Apr 2, 1998 Issued
Array ( [id] => 4069978 [patent_doc_number] => 05933744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Alignment method for used in chemical mechanical polishing process' [patent_app_type] => 1 [patent_app_number] => 9/054302 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933744.pdf [firstpage_image] =>[orig_patent_app_number] => 054302 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/054302
Alignment method for used in chemical mechanical polishing process Apr 1, 1998 Issued
09/050707 A METHOD FOR FORMING AN INTERCONNECT SYSTEM USING A LOW DIELECTRIC CONSTANT LAYER Mar 29, 1998 Abandoned
09/037290 SEMICONDUCTOR DEVICE STRUCTURE WITH HYDROGEN-RICHLAYER FOR FACILITATING PASSIVATION OF SURFACE STATES Mar 8, 1998 Abandoned
Array ( [id] => 6209424 [patent_doc_number] => 20020072230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'RESIDUE-FREE CONTACT OPENINGS AND METHODS FOR FABRICATING SAME' [patent_app_type] => new [patent_app_number] => 09/035497 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3251 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20020072230.pdf [firstpage_image] =>[orig_patent_app_number] => 09035497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/035497
Residue-free contact openings and methods for fabricating same Mar 4, 1998 Issued
Array ( [id] => 4405570 [patent_doc_number] => 06171891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method of manufacture of CMOS device using additional implant regions to enhance ESD performance' [patent_app_type] => 1 [patent_app_number] => 9/031653 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3061 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171891.pdf [firstpage_image] =>[orig_patent_app_number] => 031653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031653
Method of manufacture of CMOS device using additional implant regions to enhance ESD performance Feb 26, 1998 Issued
Array ( [id] => 4185597 [patent_doc_number] => 06093604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Method of manufacturing a flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/026550 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 2816 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093604.pdf [firstpage_image] =>[orig_patent_app_number] => 026550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026550
Method of manufacturing a flash memory device Feb 19, 1998 Issued
Array ( [id] => 4291760 [patent_doc_number] => 06180444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/025710 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6256 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180444.pdf [firstpage_image] =>[orig_patent_app_number] => 025710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025710
Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same Feb 17, 1998 Issued
Array ( [id] => 1566042 [patent_doc_number] => 06376369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Robust pressure aluminum fill process' [patent_app_type] => B1 [patent_app_number] => 09/022568 [patent_app_country] => US [patent_app_date] => 1998-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4232 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376369.pdf [firstpage_image] =>[orig_patent_app_number] => 09022568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022568
Robust pressure aluminum fill process Feb 11, 1998 Issued
09/021394 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Feb 9, 1998 Issued
Array ( [id] => 4016606 [patent_doc_number] => 05923994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Selective oxidation process' [patent_app_type] => 1 [patent_app_number] => 9/019591 [patent_app_country] => US [patent_app_date] => 1998-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6027 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923994.pdf [firstpage_image] =>[orig_patent_app_number] => 019591 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/019591
Selective oxidation process Feb 5, 1998 Issued
09/011130 A METHOD FOR THE LOW TEMPERATURE CLEANING OF SUBSTRATES CONTAINING INDIUM OR ANTIMONY Jan 29, 1998 Abandoned
Array ( [id] => 4050705 [patent_doc_number] => 05943589 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method of fabricating semiconductor device with a trench isolation' [patent_app_type] => 1 [patent_app_number] => 9/015531 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2726 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943589.pdf [firstpage_image] =>[orig_patent_app_number] => 015531 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015531
Method of fabricating semiconductor device with a trench isolation Jan 28, 1998 Issued
Array ( [id] => 4063919 [patent_doc_number] => 06008091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Floating gate avalanche injection MOS transistors with high K dielectric control gates' [patent_app_type] => 1 [patent_app_number] => 9/014030 [patent_app_country] => US [patent_app_date] => 1998-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3162 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008091.pdf [firstpage_image] =>[orig_patent_app_number] => 014030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/014030
Floating gate avalanche injection MOS transistors with high K dielectric control gates Jan 26, 1998 Issued
Array ( [id] => 1034472 [patent_doc_number] => 06875681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-05 [patent_title] => 'Wafer passivation structure and method of fabrication' [patent_app_type] => utility [patent_app_number] => 09/002178 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3259 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/875/06875681.pdf [firstpage_image] =>[orig_patent_app_number] => 09002178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002178
Wafer passivation structure and method of fabrication Dec 30, 1997 Issued
Array ( [id] => 4114117 [patent_doc_number] => 06046101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Passivation technology combining improved adhesion in passivation and a scribe street without passivation' [patent_app_type] => 1 [patent_app_number] => 9/001970 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5628 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046101.pdf [firstpage_image] =>[orig_patent_app_number] => 001970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001970
Passivation technology combining improved adhesion in passivation and a scribe street without passivation Dec 30, 1997 Issued
Array ( [id] => 3942646 [patent_doc_number] => 05946601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Unique .alpha.-C:N:H/.alpha.-C:N.sub.x film liner/barrier to prevent fluorine outdiffusion from .alpha.-FC chemical vapor deposition dielectric layers' [patent_app_type] => 1 [patent_app_number] => 9/001547 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2832 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946601.pdf [firstpage_image] =>[orig_patent_app_number] => 001547 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001547
Unique .alpha.-C:N:H/.alpha.-C:N.sub.x film liner/barrier to prevent fluorine outdiffusion from .alpha.-FC chemical vapor deposition dielectric layers Dec 30, 1997 Issued
Array ( [id] => 4182034 [patent_doc_number] => 06150206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Methods of forming integrated circuit capacitors using trench isolation and planarization techniques' [patent_app_type] => 1 [patent_app_number] => 8/996558 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 2528 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150206.pdf [firstpage_image] =>[orig_patent_app_number] => 996558 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996558
Methods of forming integrated circuit capacitors using trench isolation and planarization techniques Dec 22, 1997 Issued
Array ( [id] => 3957611 [patent_doc_number] => 05930645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Shallow trench isolation formation with reduced polish stop thickness' [patent_app_type] => 1 [patent_app_number] => 8/993881 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3759 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930645.pdf [firstpage_image] =>[orig_patent_app_number] => 993881 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993881
Shallow trench isolation formation with reduced polish stop thickness Dec 17, 1997 Issued
Array ( [id] => 4249981 [patent_doc_number] => 06207520 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Rapid thermal anneal with a gaseous dopant species for formation of lightly doped regions' [patent_app_type] => 1 [patent_app_number] => 8/993918 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3145 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207520.pdf [firstpage_image] =>[orig_patent_app_number] => 993918 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993918
Rapid thermal anneal with a gaseous dopant species for formation of lightly doped regions Dec 17, 1997 Issued
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