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Kakali Chaki

Supervisory Patent Examiner (ID: 3211, Phone: (571)272-3719 , Office: P/2122 )

Most Active Art Unit
2122
Art Unit(s)
2307, 2100, 2193, 2764, 2762, 2755, 2124, 2316, 2122, 2899
Total Applications
634
Issued Applications
396
Pending Applications
105
Abandoned Applications
133

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2831431 [patent_doc_number] => 05095427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Dispatch control of virtual machine' [patent_app_type] => 1 [patent_app_number] => 7/365694 [patent_app_country] => US [patent_app_date] => 1989-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6808 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/095/05095427.pdf [firstpage_image] =>[orig_patent_app_number] => 365694 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/365694
Dispatch control of virtual machine Jun 13, 1989 Issued
07/366774 METHOD AND APPARATUS FOR SCHEDULING TASKS IN REPEATED ITERATIONS IN A DIGITAL DATA PROCESSING SYSTEM HAVING MULTIPLE PROCESSORS Jun 12, 1989 Abandoned
07/359829 SHARED LIBRARIES IMPLEMENTED WITH LINKING PROGRAM LOADER May 31, 1989 Abandoned
07/360241 DATA PROCESSING APPARATUS May 31, 1989 Abandoned
07/357169 METHOD OF SCHEDULING TASKS WITH PRIORITY TO INTERRUPTED TASK LOCKING SHARED RESOURCE May 25, 1989 Abandoned
07/352080 FILE LOCK MANAGEMENT IN A DISTRIBUTED DATA PROCESSING SYSTEM May 14, 1989 Abandoned
07/348557 SYSTEM AND METHOD FOR READING AND WRITING DISKS FORMATTED FOR AN OPERATING SYSTEM FOREIGN TO THE HOST COMPUTER May 7, 1989 Abandoned
07/342987 STORAGE CONTROL METHOD AND APPARATUS FOR AN INTERACTIVE TELEVISION TERMINAL Apr 19, 1989 Abandoned
Array ( [id] => 2718035 [patent_doc_number] => 05041962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-20 [patent_title] => 'Computer system with means for regulating effective processing rates' [patent_app_type] => 1 [patent_app_number] => 7/338066 [patent_app_country] => US [patent_app_date] => 1989-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2015 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/041/05041962.pdf [firstpage_image] =>[orig_patent_app_number] => 338066 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/338066
Computer system with means for regulating effective processing rates Apr 13, 1989 Issued
07/335048 DUAL-PATH COMPUTER INTERCONNECT SYSTEM WITH FOUR-PORTED PACKET MEMORY CONTROL Apr 6, 1989 Abandoned
Array ( [id] => 2841434 [patent_doc_number] => 05128943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Independent backup mode transfer and mechanism for digital control computers' [patent_app_type] => 1 [patent_app_number] => 7/346247 [patent_app_country] => US [patent_app_date] => 1989-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5040 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/128/05128943.pdf [firstpage_image] =>[orig_patent_app_number] => 346247 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/346247
Independent backup mode transfer and mechanism for digital control computers Apr 4, 1989 Issued
Array ( [id] => 2716573 [patent_doc_number] => 05062036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-29 [patent_title] => 'Instruction prefetcher' [patent_app_type] => 1 [patent_app_number] => 7/333818 [patent_app_country] => US [patent_app_date] => 1989-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 11607 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/062/05062036.pdf [firstpage_image] =>[orig_patent_app_number] => 333818 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/333818
Instruction prefetcher Apr 2, 1989 Issued
07/328920 PROCESSOR INTERFACE CONTROLLER FOR INTERFACING PERIPHERAL DEVICES TO A PROCESSOR Mar 26, 1989 Abandoned
Array ( [id] => 2682660 [patent_doc_number] => 05027317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-25 [patent_title] => 'Method and circuit for limiting access to a RAM program memory' [patent_app_type] => 1 [patent_app_number] => 7/325454 [patent_app_country] => US [patent_app_date] => 1989-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4831 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/027/05027317.pdf [firstpage_image] =>[orig_patent_app_number] => 325454 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/325454
Method and circuit for limiting access to a RAM program memory Mar 16, 1989 Issued
Array ( [id] => 2841300 [patent_doc_number] => 05128936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Communication bus system and station for use in such a communication bus system' [patent_app_type] => 1 [patent_app_number] => 7/316722 [patent_app_country] => US [patent_app_date] => 1989-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3789 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/128/05128936.pdf [firstpage_image] =>[orig_patent_app_number] => 316722 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/316722
Communication bus system and station for use in such a communication bus system Feb 27, 1989 Issued
Array ( [id] => 2849969 [patent_doc_number] => 05121487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'High speed bus with virtual memory data transfer capability using virtual address/data lines' [patent_app_type] => 1 [patent_app_number] => 7/313250 [patent_app_country] => US [patent_app_date] => 1989-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5679 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121487.pdf [firstpage_image] =>[orig_patent_app_number] => 313250 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/313250
High speed bus with virtual memory data transfer capability using virtual address/data lines Feb 20, 1989 Issued
Array ( [id] => 2857795 [patent_doc_number] => 05107462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-21 [patent_title] => 'Self timed register file having bit storage cells with emitter-coupled output selectors for common bits sharing a common pull-up resistor and a common current sink' [patent_app_type] => 1 [patent_app_number] => 7/306445 [patent_app_country] => US [patent_app_date] => 1989-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9162 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/107/05107462.pdf [firstpage_image] =>[orig_patent_app_number] => 306445 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/306445
Self timed register file having bit storage cells with emitter-coupled output selectors for common bits sharing a common pull-up resistor and a common current sink Feb 2, 1989 Issued
Array ( [id] => 3089699 [patent_doc_number] => 05297255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism' [patent_app_type] => 1 [patent_app_number] => 7/303626 [patent_app_country] => US [patent_app_date] => 1989-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 34 [patent_no_of_words] => 20829 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297255.pdf [firstpage_image] =>[orig_patent_app_number] => 303626 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/303626
Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism Jan 26, 1989 Issued
Array ( [id] => 3058877 [patent_doc_number] => 05335337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-02 [patent_title] => 'Programmable data transfer timing' [patent_app_type] => 1 [patent_app_number] => 7/303624 [patent_app_country] => US [patent_app_date] => 1989-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5079 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/335/05335337.pdf [firstpage_image] =>[orig_patent_app_number] => 303624 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/303624
Programmable data transfer timing Jan 26, 1989 Issued
07/301489 PROGRAM LOADING METHOD AND SYSTEM FOR DISTRIBUTED PROCESSING SYSTEM Jan 25, 1989 Abandoned
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