Kakali Chaki

Array ( [id] => 3080093 [patent_doc_number] => 05323037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-21 [patent_title] => 'Layered capacitor structure for a dynamic random access memory device' [patent_app_type] => 1 [patent_app_number] => 8/042642 [patent_app_country] => US [patent_app_date] => 1993-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2263 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/323/05323037.pdf [firstpage_image] =>[orig_patent_app_number] => 042642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2994986 [patent_doc_number] => 05347150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Semiconductor input/output circuits operating at different power supply voltages' [patent_app_type] => 1 [patent_app_number] => 8/039666 [patent_app_country] => US [patent_app_date] => 1993-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 6236 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/347/05347150.pdf [firstpage_image] =>[orig_patent_app_number] => 039666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3019567 [patent_doc_number] => 05341011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Short channel trenched DMOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/031798 [patent_app_country] => US [patent_app_date] => 1993-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2745 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341011.pdf [firstpage_image] =>[orig_patent_app_number] => 031798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3463564 [patent_doc_number] => 05382817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-17 [patent_title] => 'Semiconductor device having a ferroelectric capacitor with a planarized lower electrode' [patent_app_type] => 1 [patent_app_number] => 8/020082 [patent_app_country] => US [patent_app_date] => 1993-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 88 [patent_no_of_words] => 13519 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/382/05382817.pdf [firstpage_image] =>[orig_patent_app_number] => 020082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3033151 [patent_doc_number] => 05349222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Single gate MOS type nonvolatile memory and operating method thereof' [patent_app_type] => 1 [patent_app_number] => 8/012882 [patent_app_country] => US [patent_app_date] => 1993-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5174 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349222.pdf [firstpage_image] =>[orig_patent_app_number] => 012882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3061653 [patent_doc_number] => 05338954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Semiconductor memory device having an insulating film and a trap film joined in a channel region' [patent_app_type] => 1 [patent_app_number] => 8/012654 [patent_app_country] => US [patent_app_date] => 1993-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5713 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/338/05338954.pdf [firstpage_image] =>[orig_patent_app_number] => 012654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3061727 [patent_doc_number] => 05338958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Semicondcutor device with high speed field effect transistor structure reducing concentrations of electric field near drain region' [patent_app_type] => 1 [patent_app_number] => 8/010284 [patent_app_country] => US [patent_app_date] => 1993-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2597 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/338/05338958.pdf [firstpage_image] =>[orig_patent_app_number] => 010284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3103862 [patent_doc_number] => 05315140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'Semiconductor device having a polysilicon capacitor with large grain diameter' [patent_app_type] => 1 [patent_app_number] => 8/008020 [patent_app_country] => US [patent_app_date] => 1993-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 55 [patent_no_of_words] => 10717 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315140.pdf [firstpage_image] =>[orig_patent_app_number] => 008020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3061672 [patent_doc_number] => 05338955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Semiconductor device having stacked type capacitor' [patent_app_type] => 1 [patent_app_number] => 8/006870 [patent_app_country] => US [patent_app_date] => 1993-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 78 [patent_no_of_words] => 12804 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/338/05338955.pdf [firstpage_image] =>[orig_patent_app_number] => 006870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3024996 [patent_doc_number] => 05327003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Semiconductor static RAM having thin film transistor gate connection' [patent_app_type] => 1 [patent_app_number] => 8/005186 [patent_app_country] => US [patent_app_date] => 1993-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 61 [patent_no_of_words] => 11325 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327003.pdf [firstpage_image] =>[orig_patent_app_number] => 005186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3019548 [patent_doc_number] => 05341010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Semiconductor device including nonvolatile memories' [patent_app_type] => 1 [patent_app_number] => 8/002606 [patent_app_country] => US [patent_app_date] => 1993-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 5811 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341010.pdf [firstpage_image] =>[orig_patent_app_number] => 002606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3061441 [patent_doc_number] => 05338942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Semiconductor projections having layers with different lattice constants' [patent_app_type] => 1 [patent_app_number] => 8/000090 [patent_app_country] => US [patent_app_date] => 1993-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 4925 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/338/05338942.pdf [firstpage_image] =>[orig_patent_app_number] => 000090 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2998511 [patent_doc_number] => 05367185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Non-volatile semiconductor memory with third electrode covering control gate' [patent_app_type] => 1 [patent_app_number] => 8/000555 [patent_app_country] => US [patent_app_date] => 1993-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3430 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367185.pdf [firstpage_image] =>[orig_patent_app_number] => 000555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3420039 [patent_doc_number] => 05393992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Semiconductor thin film transistor with gate controlled offset portion' [patent_app_type] => 1 [patent_app_number] => 7/997678 [patent_app_country] => US [patent_app_date] => 1992-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3500 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/393/05393992.pdf [firstpage_image] =>[orig_patent_app_number] => 997678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3019469 [patent_doc_number] => 05341006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Semiconductor device having diffusion-preventing layer between III-V layer and IV layer' [patent_app_type] => 1 [patent_app_number] => 7/992042 [patent_app_country] => US [patent_app_date] => 1992-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2584 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341006.pdf [firstpage_image] =>[orig_patent_app_number] => 992042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3040613 [patent_doc_number] => 05300803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Source side injection non-volatile memory cell' [patent_app_type] => 1 [patent_app_number] => 7/992858 [patent_app_country] => US [patent_app_date] => 1992-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2105 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/300/05300803.pdf [firstpage_image] =>[orig_patent_app_number] => 992858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3049901 [patent_doc_number] => 05334866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-02 [patent_title] => 'Integrated circuit device with functions selectable by changing interconnection pattern' [patent_app_type] => 1 [patent_app_number] => 7/989446 [patent_app_country] => US [patent_app_date] => 1992-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2428 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/334/05334866.pdf [firstpage_image] =>[orig_patent_app_number] => 989446 [rel_patent_id] =>[rel_patent_doc_number] =>)