| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 18125248
[patent_doc_number] => 20230010863
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-12
[patent_title] => INTERMODAL CALLING BRANCH INSTRUCTION
[patent_app_type] => utility
[patent_app_number] => 17/757197
[patent_app_country] => US
[patent_app_date] => 2020-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 37306
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17757197
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/757197 | Intermodal calling branch instruction | Nov 4, 2020 | Issued |
Array
(
[id] => 17744320
[patent_doc_number] => 11392387
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-19
[patent_title] => Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor
[patent_app_type] => utility
[patent_app_number] => 17/089379
[patent_app_country] => US
[patent_app_date] => 2020-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 15790
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 319
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089379
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/089379 | Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor | Nov 3, 2020 | Issued |
Array
(
[id] => 16794772
[patent_doc_number] => 20210124589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-29
[patent_title] => EVENT HANDLING IN PIPELINE EXECUTE STAGES
[patent_app_type] => utility
[patent_app_number] => 17/079105
[patent_app_country] => US
[patent_app_date] => 2020-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9666
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079105
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/079105 | Storing a result of a first instruction of an execute packet in a holding register prior to completion of a second instruction of the execute packet | Oct 22, 2020 | Issued |
Array
(
[id] => 17408884
[patent_doc_number] => 11249766
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-02-15
[patent_title] => Coprocessor synchronizing instruction suppression
[patent_app_type] => utility
[patent_app_number] => 17/077654
[patent_app_country] => US
[patent_app_date] => 2020-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 13630
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077654
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/077654 | Coprocessor synchronizing instruction suppression | Oct 21, 2020 | Issued |
Array
(
[id] => 17550101
[patent_doc_number] => 20220121443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => THREAD-BASED PROCESSOR HALTING
[patent_app_type] => utility
[patent_app_number] => 17/074730
[patent_app_country] => US
[patent_app_date] => 2020-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12153
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074730
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/074730 | Thread-based processor halting | Oct 19, 2020 | Issued |
Array
(
[id] => 16751434
[patent_doc_number] => 20210103443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-08
[patent_title] => ENHANCED SECURITY COMPUTER PROCESSOR WITH MENTOR CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 17/074491
[patent_app_country] => US
[patent_app_date] => 2020-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 39821
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074491
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/074491 | ENHANCED SECURITY COMPUTER PROCESSOR WITH MENTOR CIRCUITS | Oct 18, 2020 | Abandoned |
Array
(
[id] => 16659297
[patent_doc_number] => 20210055934
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-25
[patent_title] => ARRAY-BASED INFERENCE ENGINE FOR MACHINE LEARNING
[patent_app_type] => utility
[patent_app_number] => 16/948867
[patent_app_country] => US
[patent_app_date] => 2020-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12781
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948867
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/948867 | ARRAY-BASED INFERENCE ENGINE FOR MACHINE LEARNING | Oct 1, 2020 | Abandoned |
Array
(
[id] => 17507414
[patent_doc_number] => 20220100517
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-31
[patent_title] => SM4 NEW INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 17/033741
[patent_app_country] => US
[patent_app_date] => 2020-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12892
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033741
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/033741 | SM4 NEW INSTRUCTIONS | Sep 25, 2020 | Abandoned |
Array
(
[id] => 18430376
[patent_doc_number] => 11675595
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Starting reading of instructions from a correct speculative condition prior to fully flushing an instruction pipeline after an incorrect instruction speculation determination
[patent_app_type] => utility
[patent_app_number] => 17/031397
[patent_app_country] => US
[patent_app_date] => 2020-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 11343
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 473
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031397
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/031397 | Starting reading of instructions from a correct speculative condition prior to fully flushing an instruction pipeline after an incorrect instruction speculation determination | Sep 23, 2020 | Issued |
Array
(
[id] => 16722158
[patent_doc_number] => 20210089305
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => INSTRUCTION EXECUTING METHOD AND APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/028352
[patent_app_country] => US
[patent_app_date] => 2020-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9614
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028352
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/028352 | INSTRUCTION EXECUTING METHOD AND APPARATUS | Sep 21, 2020 | Abandoned |
Array
(
[id] => 17462319
[patent_doc_number] => 20220075624
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => ALTERNATE PATH FOR BRANCH PREDICTION REDIRECT
[patent_app_type] => utility
[patent_app_number] => 17/012833
[patent_app_country] => US
[patent_app_date] => 2020-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8543
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17012833
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/012833 | ALTERNATE PATH FOR BRANCH PREDICTION REDIRECT | Sep 3, 2020 | Abandoned |
Array
(
[id] => 17984571
[patent_doc_number] => 20220350608
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => BRANCH PREDICTION CIRCUIT AND INSTRUCTION PROCESSING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/761293
[patent_app_country] => US
[patent_app_date] => 2020-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6041
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17761293
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/761293 | BRANCH PREDICTION CIRCUIT AND INSTRUCTION PROCESSING METHOD | Sep 1, 2020 | Abandoned |
Array
(
[id] => 16514780
[patent_doc_number] => 20200394038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-17
[patent_title] => LOOK UP TABLE WITH DATA ELEMENT PROMOTION
[patent_app_type] => utility
[patent_app_number] => 17/008456
[patent_app_country] => US
[patent_app_date] => 2020-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16157
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008456
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/008456 | Look up table with data element promotion | Aug 30, 2020 | Issued |
Array
(
[id] => 16508119
[patent_doc_number] => 20200387375
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-10
[patent_title] => INSTRUCTION DEMARCATOR
[patent_app_type] => utility
[patent_app_number] => 16/991408
[patent_app_country] => US
[patent_app_date] => 2020-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14321
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16991408
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/991408 | Instruction length based parallel instruction demarcator | Aug 11, 2020 | Issued |
Array
(
[id] => 16630473
[patent_doc_number] => 20210049126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => RECONFIGURABLE PARALLEL PROCESSING
[patent_app_type] => utility
[patent_app_number] => 16/932039
[patent_app_country] => US
[patent_app_date] => 2020-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21834
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932039
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/932039 | Reconfigurable parallel processing with various reconfigurable units to form two or more physical data paths and routing data from one physical data path to a gasket memory to be used in a future physical data path as input | Jul 16, 2020 | Issued |
Array
(
[id] => 17238456
[patent_doc_number] => 11182336
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-23
[patent_title] => Reconfigurable parallel processing with a temporary data storage coupled to a plurality of processing elements (PES) to store a PE execution result to be used by a PE during a next PE configuration
[patent_app_type] => utility
[patent_app_number] => 16/931993
[patent_app_country] => US
[patent_app_date] => 2020-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 35
[patent_no_of_words] => 21844
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931993
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/931993 | Reconfigurable parallel processing with a temporary data storage coupled to a plurality of processing elements (PES) to store a PE execution result to be used by a PE during a next PE configuration | Jul 16, 2020 | Issued |
Array
(
[id] => 16486339
[patent_doc_number] => 20200379945
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-03
[patent_title] => CIRCULAR RECONFIGURATION FOR RECONFIGURABLE PARALLEL PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 16/931546
[patent_app_country] => US
[patent_app_date] => 2020-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20042
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931546
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/931546 | Circular reconfiguration for reconfigurable parallel processor using a plurality of memory ports coupled to a commonly accessible memory unit | Jul 16, 2020 | Issued |
Array
(
[id] => 16486338
[patent_doc_number] => 20200379944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-03
[patent_title] => Shared Memory Structure for Reconfigurable Parallel Processor
[patent_app_type] => utility
[patent_app_number] => 16/930472
[patent_app_country] => US
[patent_app_date] => 2020-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19827
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16930472
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/930472 | Shared memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit | Jul 15, 2020 | Issued |
Array
(
[id] => 17316958
[patent_doc_number] => 20210406007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => GENERATING OPTIMIZED MICROCODE INSTRUCTIONS FOR DYNAMIC PROGRAMMING BASED ON IDEMPOTENT SEMIRING OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 16/917654
[patent_app_country] => US
[patent_app_date] => 2020-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12618
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917654
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/917654 | GENERATING OPTIMIZED MICROCODE INSTRUCTIONS FOR DYNAMIC PROGRAMMING BASED ON IDEMPOTENT SEMIRING OPERATIONS | Jun 29, 2020 | Abandoned |
Array
(
[id] => 17316960
[patent_doc_number] => 20210406009
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => APPARATUS FOR OPTIMIZED MICROCODE INSTRUCTIONS FOR DYNAMIC PROGRAMMING BASED ON IDEMPOTENT SEMIRING OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 16/917634
[patent_app_country] => US
[patent_app_date] => 2020-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12617
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917634
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/917634 | APPARATUS FOR OPTIMIZED MICROCODE INSTRUCTIONS FOR DYNAMIC PROGRAMMING BASED ON IDEMPOTENT SEMIRING OPERATIONS | Jun 29, 2020 | Abandoned |