Search

Kamal B. Divecha

Supervisory Patent Examiner (ID: 15210, Phone: (571)272-5863 , Office: P/2453 )

Most Active Art Unit
2451
Art Unit(s)
2455, 2451, 2446, 2151, 2453
Total Applications
305
Issued Applications
61
Pending Applications
22
Abandoned Applications
222

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17238453 [patent_doc_number] => 11182333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Private memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit [patent_app_type] => utility [patent_app_number] => 16/906352 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 19846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906352
Private memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit Jun 18, 2020 Issued
Array ( [id] => 16787977 [patent_doc_number] => 10990410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 16/864896 [patent_app_country] => US [patent_app_date] => 2020-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16864896 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/864896
Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit Apr 30, 2020 Issued
Array ( [id] => 18095515 [patent_doc_number] => 20220413856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => INSTRUCTION EXECUTION METHOD, APPARATUS AND DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/780809 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17780809 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/780809
INSTRUCTION EXECUTION METHOD, APPARATUS AND DEVICE, AND STORAGE MEDIUM Apr 26, 2020 Abandoned
Array ( [id] => 17877330 [patent_doc_number] => 11449344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-20 [patent_title] => Regular expression processor and parallel processing architecture [patent_app_type] => utility [patent_app_number] => 16/854441 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 13146 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854441 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854441
Regular expression processor and parallel processing architecture Apr 20, 2020 Issued
Array ( [id] => 17128540 [patent_doc_number] => 20210303309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => RECONSTRUCTION OF FLAGS AND DATA FOR IMMEDIATE FOLDING [patent_app_type] => utility [patent_app_number] => 16/833072 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833072 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833072
RECONSTRUCTION OF FLAGS AND DATA FOR IMMEDIATE FOLDING Mar 26, 2020 Abandoned
Array ( [id] => 18873410 [patent_doc_number] => 11861220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Allocation of memory by mapping registers referenced by different instances of a task to individual logical memories [patent_app_type] => utility [patent_app_number] => 16/791323 [patent_app_country] => US [patent_app_date] => 2020-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 10105 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16791323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/791323
Allocation of memory by mapping registers referenced by different instances of a task to individual logical memories Feb 13, 2020 Issued
Array ( [id] => 16409261 [patent_doc_number] => 10817820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Facilitating provisioning in a mixed environment of locales [patent_app_type] => utility [patent_app_number] => 16/786997 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3342 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786997
Facilitating provisioning in a mixed environment of locales Feb 9, 2020 Issued
Array ( [id] => 16065029 [patent_doc_number] => 10691464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-23 [patent_title] => Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 16/747976 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747976 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747976
Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit Jan 20, 2020 Issued
Array ( [id] => 15902889 [patent_doc_number] => 20200150964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => LIVELOCK RECOVERY CIRCUIT FOR DETECTING ILLEGAL REPETITION OF AN INSTRUCTION AND TRANSITIONING TO A KNOWN STATE [patent_app_type] => utility [patent_app_number] => 16/743586 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743586 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743586
Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known state Jan 14, 2020 Issued
Array ( [id] => 18982535 [patent_doc_number] => 11907713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator [patent_app_type] => utility [patent_app_number] => 16/729369 [patent_app_country] => US [patent_app_date] => 2019-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 97 [patent_figures_cnt] => 133 [patent_no_of_words] => 85525 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/729369
Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator Dec 27, 2019 Issued
Array ( [id] => 16934661 [patent_doc_number] => 20210200550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => LOOP EXIT PREDICTOR [patent_app_type] => utility [patent_app_number] => 16/729367 [patent_app_country] => US [patent_app_date] => 2019-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729367 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/729367
LOOP EXIT PREDICTOR Dec 27, 2019 Abandoned
Array ( [id] => 16934660 [patent_doc_number] => 20210200549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SYSTEMS, APPARATUSES, AND METHODS FOR 512-BIT OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/728785 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728785 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728785
SYSTEMS, APPARATUSES, AND METHODS FOR 512-BIT OPERATIONS Dec 26, 2019 Abandoned
Array ( [id] => 16385177 [patent_doc_number] => 10810012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => Computer vision implementing calculations of window sums in overlapping windows [patent_app_type] => utility [patent_app_number] => 16/720808 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720808
Computer vision implementing calculations of window sums in overlapping windows Dec 18, 2019 Issued
Array ( [id] => 16017701 [patent_doc_number] => 20200183694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => CALCULATION PROCESSING APPARATUS AND METHOD OF CONTROLLING CALCULATION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/697244 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697244 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697244
Inhibiting load instruction execution based on reserving a resource of a load and store queue but failing to reserve a resource of a store data queue Nov 26, 2019 Issued
Array ( [id] => 16856852 [patent_doc_number] => 20210157597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SPECULATIVE BUFFER [patent_app_type] => utility [patent_app_number] => 16/695735 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695735 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695735
Speculative buffer for speculative memory accesses with entries tagged with execution context identifiers Nov 25, 2019 Issued
Array ( [id] => 16856856 [patent_doc_number] => 20210157601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => EXCEPTION INTERCEPTION [patent_app_type] => utility [patent_app_number] => 16/695745 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695745
Exception interception Nov 25, 2019 Issued
Array ( [id] => 16856853 [patent_doc_number] => 20210157598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => REGISTER WRITE SUPPRESSION [patent_app_type] => utility [patent_app_number] => 16/697147 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697147 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697147
Suppressing allocation of registers for register renaming Nov 25, 2019 Issued
Array ( [id] => 17454791 [patent_doc_number] => 11269650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Pipeline protection for CPUs with save and restore of intermediate results [patent_app_type] => utility [patent_app_number] => 16/685747 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9101 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685747 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685747
Pipeline protection for CPUs with save and restore of intermediate results Nov 14, 2019 Issued
Array ( [id] => 16116337 [patent_doc_number] => 20200210191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => EXIT HISTORY BASED BRANCH PREDICTION [patent_app_type] => utility [patent_app_number] => 16/684410 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684410
Exit history based branch prediction Nov 13, 2019 Issued
Array ( [id] => 16299882 [patent_doc_number] => 20200285605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => SYSTOLIC ARRAY AND PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/684246 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684246 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684246
MxN systolic array and processing system that inputs weights to rows or columns based on mode to increase utilization of processing elements Nov 13, 2019 Issued
Menu