Search

Kamini S. Shah

Supervisory Patent Examiner (ID: 9613, Phone: (571)272-2279 , Office: P/2123 )

Most Active Art Unit
2857
Art Unit(s)
2414, 2764, 2127, 2863, 2116, 2314, 2128, 2211, 2123, 2857, 2146, 2115, 2142
Total Applications
939
Issued Applications
692
Pending Applications
104
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18155917 [patent_doc_number] => 11568906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters [patent_app_type] => utility [patent_app_number] => 17/301531 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301531 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301531
Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters Apr 5, 2021 Issued
Array ( [id] => 17977466 [patent_doc_number] => 11494326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Programmable computations in direct memory access engine [patent_app_type] => utility [patent_app_number] => 17/301273 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13944 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301273
Programmable computations in direct memory access engine Mar 29, 2021 Issued
Array ( [id] => 17924584 [patent_doc_number] => 11467832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Vector floating-point classification [patent_app_type] => utility [patent_app_number] => 17/215032 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 10950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215032
Vector floating-point classification Mar 28, 2021 Issued
Array ( [id] => 17899217 [patent_doc_number] => 20220308879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => Accelerator Interface Mechanism for Data Processing System [patent_app_type] => utility [patent_app_number] => 17/209606 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209606 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209606
Accelerator interface mechanism for data processing system Mar 22, 2021 Issued
Array ( [id] => 17542878 [patent_doc_number] => 11308001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-19 [patent_title] => Dynamically provisioning peripherals to containers [patent_app_type] => utility [patent_app_number] => 17/205343 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 8 [patent_no_of_words] => 5911 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205343 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/205343
Dynamically provisioning peripherals to containers Mar 17, 2021 Issued
Array ( [id] => 19971685 [patent_doc_number] => 12340300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-24 [patent_title] => Streaming processor architecture [patent_app_type] => utility [patent_app_number] => 17/203214 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 10509 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17203214 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/203214
Streaming processor architecture Mar 15, 2021 Issued
Array ( [id] => 18119226 [patent_doc_number] => 11550620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Task dispatch [patent_app_type] => utility [patent_app_number] => 17/190729 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 14282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190729 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190729
Task dispatch Mar 2, 2021 Issued
Array ( [id] => 17651535 [patent_doc_number] => 11354264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Bimodal PHY for low latency in high speed interconnects [patent_app_type] => utility [patent_app_number] => 17/184737 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 12958 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184737
Bimodal PHY for low latency in high speed interconnects Feb 24, 2021 Issued
Array ( [id] => 17809417 [patent_doc_number] => 20220261252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => CIRCUITRY AND METHOD [patent_app_type] => utility [patent_app_number] => 17/175150 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17175150 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/175150
Circuitry and method Feb 11, 2021 Issued
Array ( [id] => 17757410 [patent_doc_number] => 11397702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Interfacing a number of serial communication interfaces with a parallel communication interface, and related systems, methods, and apparatuses [patent_app_type] => utility [patent_app_number] => 17/171697 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8637 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171697 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171697
Interfacing a number of serial communication interfaces with a parallel communication interface, and related systems, methods, and apparatuses Feb 8, 2021 Issued
Array ( [id] => 17128723 [patent_doc_number] => 20210303492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => FAULT TOLERANT SYSTEM [patent_app_type] => utility [patent_app_number] => 17/166499 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/166499
Fault tolerant system Feb 2, 2021 Issued
Array ( [id] => 20145615 [patent_doc_number] => 12379957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Onboard ECU, information processing method, and onboard system [patent_app_type] => utility [patent_app_number] => 17/760400 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4807 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17760400 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/760400
Onboard ECU, information processing method, and onboard system Jan 25, 2021 Issued
Array ( [id] => 17636782 [patent_doc_number] => 11347506 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-31 [patent_title] => Memory copy size determining instruction and data transfer instruction [patent_app_type] => utility [patent_app_number] => 17/149860 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12827 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149860 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149860
Memory copy size determining instruction and data transfer instruction Jan 14, 2021 Issued
Array ( [id] => 17736741 [patent_doc_number] => 20220222200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => TIMED-TRIGGER SYNCHRONIZATION ENHANCEMENT [patent_app_type] => utility [patent_app_number] => 17/148953 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148953 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148953
Timed-trigger synchronization enhancement Jan 13, 2021 Issued
Array ( [id] => 18873555 [patent_doc_number] => 11861369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Processing-in-memory (PIM) device [patent_app_type] => utility [patent_app_number] => 17/149622 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 60 [patent_no_of_words] => 54089 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149622 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149622
Processing-in-memory (PIM) device Jan 13, 2021 Issued
Array ( [id] => 19414424 [patent_doc_number] => 12080256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Electronic device and control method thereof [patent_app_type] => utility [patent_app_number] => 17/144959 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144959 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144959
Electronic device and control method thereof Jan 7, 2021 Issued
Array ( [id] => 17999522 [patent_doc_number] => 11500629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Processing-in-memory (PIM) system including multiplying-and-accumulating (MAC) circuit [patent_app_type] => utility [patent_app_number] => 17/144530 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 26478 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144530 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144530
Processing-in-memory (PIM) system including multiplying-and-accumulating (MAC) circuit Jan 7, 2021 Issued
Array ( [id] => 19327925 [patent_doc_number] => 12045613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Vector data processing method and system, computing node, and storage medium [patent_app_type] => utility [patent_app_number] => 18/041440 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18041440 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/041440
Vector data processing method and system, computing node, and storage medium Dec 30, 2020 Issued
Array ( [id] => 17423084 [patent_doc_number] => 11256538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Directed interrupt virtualization with interrupt table [patent_app_type] => utility [patent_app_number] => 17/137755 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 34 [patent_no_of_words] => 25921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137755
Directed interrupt virtualization with interrupt table Dec 29, 2020 Issued
Array ( [id] => 16780286 [patent_doc_number] => 20210117365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHOD FOR INTERFACE INITIALIZATION USING BUS TURN-AROUND [patent_app_type] => utility [patent_app_number] => 17/134293 [patent_app_country] => US [patent_app_date] => 2020-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134293 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134293
Method for interface initialization using bus turn-around Dec 25, 2020 Issued
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