Search

Kamini S. Shah

Supervisory Patent Examiner (ID: 9613, Phone: (571)272-2279 , Office: P/2123 )

Most Active Art Unit
2857
Art Unit(s)
2414, 2764, 2127, 2863, 2116, 2314, 2128, 2211, 2123, 2857, 2146, 2115, 2142
Total Applications
939
Issued Applications
692
Pending Applications
104
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19152989 [patent_doc_number] => 11977902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Methods and systems for event reporting [patent_app_type] => utility [patent_app_number] => 16/885996 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 21257 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885996 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885996
Methods and systems for event reporting May 27, 2020 Issued
Array ( [id] => 16486170 [patent_doc_number] => 20200379775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => TECHNIQUES FOR ACCELERATING COMPACTION [patent_app_type] => utility [patent_app_number] => 16/885112 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885112 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885112
Techniques for accelerating compaction May 26, 2020 Issued
Array ( [id] => 17589488 [patent_doc_number] => 11327761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Processing device with vector transformation execution [patent_app_type] => utility [patent_app_number] => 16/881327 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6790 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881327 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/881327
Processing device with vector transformation execution May 21, 2020 Issued
Array ( [id] => 16714057 [patent_doc_number] => 20210081204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => MEMORY MODULE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/879120 [patent_app_country] => US [patent_app_date] => 2020-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16879120 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/879120
Memory module and operating method thereof May 19, 2020 Issued
Array ( [id] => 17230710 [patent_doc_number] => 20210357267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => DEFINING AND ACCESSING DYNAMIC REGISTERS IN A VIRTUAL MULTI-PROCESSOR SYSTEM [patent_app_type] => utility [patent_app_number] => 16/874993 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874993
DEFINING AND ACCESSING DYNAMIC REGISTERS IN A VIRTUAL MULTI-PROCESSOR SYSTEM May 14, 2020 Abandoned
Array ( [id] => 17729406 [patent_doc_number] => 11385793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Methods and apparatus to manage workload memory allocation [patent_app_type] => utility [patent_app_number] => 16/870428 [patent_app_country] => US [patent_app_date] => 2020-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8000 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16870428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/870428
Methods and apparatus to manage workload memory allocation May 7, 2020 Issued
Array ( [id] => 18072773 [patent_doc_number] => 11531607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Fault isolation and recovery of CPU cores for failed secondary asymmetric multiprocessing instance [patent_app_type] => utility [patent_app_number] => 16/854302 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854302 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854302
Fault isolation and recovery of CPU cores for failed secondary asymmetric multiprocessing instance Apr 20, 2020 Issued
Array ( [id] => 16347736 [patent_doc_number] => 20200312387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => APPARATUSES AND METHODS FOR STORING AND WRITING MULTIPLE PARAMETER CODES FOR MEMORY OPERATING PARAMETERS [patent_app_type] => utility [patent_app_number] => 16/853917 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853917 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/853917
Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters Apr 20, 2020 Issued
Array ( [id] => 16454622 [patent_doc_number] => 20200364048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => METHOD AND APPARATUS FOR PROCESSING DATA SPLICING INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/845499 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845499 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845499
Method and apparatus for processing data splicing instruction Apr 9, 2020 Issued
Array ( [id] => 17720946 [patent_doc_number] => 20220213666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => REMOTE OPERATION SYSTEM AND REMOTE OPERATION SERVER [patent_app_type] => utility [patent_app_number] => 17/611704 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17611704 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/611704
Remote operation system and remote operation server Apr 8, 2020 Issued
Array ( [id] => 17143728 [patent_doc_number] => 20210311741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => PROCESSOR HAVING READ SHIFTER AND CONTROLLING METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/842684 [patent_app_country] => US [patent_app_date] => 2020-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16842684 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/842684
Processor having read shifter and controlling method using the same Apr 6, 2020 Issued
Array ( [id] => 16972459 [patent_doc_number] => 11068431 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-20 [patent_title] => Edge component redirect for IoT analytics groups [patent_app_type] => utility [patent_app_number] => 16/838288 [patent_app_country] => US [patent_app_date] => 2020-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16838288 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/838288
Edge component redirect for IoT analytics groups Apr 1, 2020 Issued
Array ( [id] => 16179123 [patent_doc_number] => 20200226091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => TRANSACTION LAYER PACKET FORMAT [patent_app_type] => utility [patent_app_number] => 16/831634 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831634 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831634
Transaction layer packet format Mar 25, 2020 Issued
Array ( [id] => 16192954 [patent_doc_number] => 20200233803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => EFFICIENT HARDWARE ARCHITECTURE FOR ACCELERATING GROUPED CONVOLUTIONS [patent_app_type] => utility [patent_app_number] => 16/830457 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830457 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/830457
Efficient hardware architecture for accelerating grouped convolutions Mar 25, 2020 Issued
Array ( [id] => 16165403 [patent_doc_number] => 20200220934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => HARDWARE TURNSTILE [patent_app_type] => utility [patent_app_number] => 16/827313 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16827313 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/827313
Hardware turnstile Mar 22, 2020 Issued
Array ( [id] => 19167626 [patent_doc_number] => 11983535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Artificial intelligence computing device and related product [patent_app_type] => utility [patent_app_number] => 17/440529 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 10741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17440529 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/440529
Artificial intelligence computing device and related product Mar 19, 2020 Issued
Array ( [id] => 17114166 [patent_doc_number] => 20210294763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => METHOD TO OVERLOAD HARDWARE PIN FOR IMPROVED SYSTEM MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/823316 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823316 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/823316
Method to overload hardware pin for improved system management Mar 17, 2020 Issued
Array ( [id] => 17269317 [patent_doc_number] => 11194744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => In-line memory module (IMM) computing node with an embedded processor(s) to support local processing of memory-based operations for lower latency and reduced power consumption [patent_app_type] => utility [patent_app_number] => 16/820572 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 12497 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16820572 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/820572
In-line memory module (IMM) computing node with an embedded processor(s) to support local processing of memory-based operations for lower latency and reduced power consumption Mar 15, 2020 Issued
Array ( [id] => 17565117 [patent_doc_number] => 20220129266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUCT ACCUMULATE INSTRUCTION FOR HYBRID FLOATING POINT FORMAT [patent_app_type] => utility [patent_app_number] => 17/428523 [patent_app_country] => US [patent_app_date] => 2020-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17428523 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/428523
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format Mar 13, 2020 Issued
Array ( [id] => 16401065 [patent_doc_number] => 20200341923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => INFORMATION PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/817011 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16817011 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/817011
INFORMATION PROCESSING SYSTEM Mar 11, 2020 Abandoned
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