Search

Kamini S. Shah

Supervisory Patent Examiner (ID: 9613, Phone: (571)272-2279 , Office: P/2123 )

Most Active Art Unit
2857
Art Unit(s)
2414, 2764, 2127, 2863, 2116, 2314, 2128, 2211, 2123, 2857, 2146, 2115, 2142
Total Applications
939
Issued Applications
692
Pending Applications
104
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16565716 [patent_doc_number] => 10891084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Apparatus and method for providing data to a master device [patent_app_type] => utility [patent_app_number] => 16/353257 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6440 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16353257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/353257
Apparatus and method for providing data to a master device Mar 13, 2019 Issued
Array ( [id] => 14570399 [patent_doc_number] => 20190212806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => STORAGE DEVICE HAVING A SERIAL COMMUNICATION PORT [patent_app_type] => utility [patent_app_number] => 16/352245 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352245 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352245
Storage device having a serial communication port Mar 12, 2019 Issued
Array ( [id] => 14585359 [patent_doc_number] => 20190220288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => INTEGRATED CIRCUIT DEVICE INCLUDING WAKE-UP CONTROL CIRCUIT AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/352185 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352185 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352185
Integrated circuit device including wake-up control circuit and electronic device including the same Mar 12, 2019 Issued
Array ( [id] => 18644653 [patent_doc_number] => 11768721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Processing device [patent_app_type] => utility [patent_app_number] => 17/040686 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9340 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17040686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/040686
Processing device Mar 11, 2019 Issued
Array ( [id] => 16758498 [patent_doc_number] => 10977046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Indirection-based process management [patent_app_type] => utility [patent_app_number] => 16/292434 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292434 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292434
Indirection-based process management Mar 4, 2019 Issued
Array ( [id] => 16478362 [patent_doc_number] => 10853310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Call stack sampling [patent_app_type] => utility [patent_app_number] => 16/292596 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292596 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292596
Call stack sampling Mar 4, 2019 Issued
Array ( [id] => 16299754 [patent_doc_number] => 20200285477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => BRANCH PREDICTOR [patent_app_type] => utility [patent_app_number] => 16/292534 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292534 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292534
Branch predictor Mar 4, 2019 Issued
Array ( [id] => 16299749 [patent_doc_number] => 20200285472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => Context-Switching Method and Apparatus [patent_app_type] => utility [patent_app_number] => 16/291059 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291059
Context-Switching Method and Apparatus Mar 3, 2019 Abandoned
Array ( [id] => 16698604 [patent_doc_number] => 10949201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Processor with accelerated lock instruction operation [patent_app_type] => utility [patent_app_number] => 16/286702 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6365 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286702 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286702
Processor with accelerated lock instruction operation Feb 26, 2019 Issued
Array ( [id] => 16446794 [patent_doc_number] => 10838723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Speculative writes to special-purpose register [patent_app_type] => utility [patent_app_number] => 16/288083 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16288083 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/288083
Speculative writes to special-purpose register Feb 26, 2019 Issued
Array ( [id] => 16271108 [patent_doc_number] => 20200272596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SYSTOLIC ARRAY ACCELERATOR SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 16/283795 [patent_app_country] => US [patent_app_date] => 2019-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283795 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/283795
Systolic array accelerator systems and methods Feb 23, 2019 Issued
Array ( [id] => 14750841 [patent_doc_number] => 20190258594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET AND CONFIGURED FOR INCREASED PERFORMANCE [patent_app_type] => utility [patent_app_number] => 16/283597 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283597 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/283597
Extended platform with additional memory module slots per CPU socket and configured for increased performance Feb 21, 2019 Issued
Array ( [id] => 16615709 [patent_doc_number] => 20210034362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => DATA PROCESSING [patent_app_type] => utility [patent_app_number] => 16/975486 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16975486 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/975486
Data processing Feb 14, 2019 Issued
Array ( [id] => 16145865 [patent_doc_number] => 10706003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Reduced pin count interface [patent_app_type] => utility [patent_app_number] => 16/266992 [patent_app_country] => US [patent_app_date] => 2019-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 19085 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16266992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/266992
Reduced pin count interface Feb 3, 2019 Issued
Array ( [id] => 16223517 [patent_doc_number] => 20200248634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => SYSTEM AND METHOD FOR MONITORING COMPONENT INTEGRITY DURING ENGINE OPERATION [patent_app_type] => utility [patent_app_number] => 16/263337 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16263337 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/263337
System and method for monitoring component integrity during engine operation Jan 30, 2019 Issued
Array ( [id] => 15297627 [patent_doc_number] => 20190391949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => METHOD FOR INTERFACE INITIALIZATION USING BUS TURNAROUND [patent_app_type] => utility [patent_app_number] => 16/254266 [patent_app_country] => US [patent_app_date] => 2019-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16254266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/254266
Method for interface initialization using bus turn-around Jan 21, 2019 Issued
Array ( [id] => 15297627 [patent_doc_number] => 20190391949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => METHOD FOR INTERFACE INITIALIZATION USING BUS TURNAROUND [patent_app_type] => utility [patent_app_number] => 16/254266 [patent_app_country] => US [patent_app_date] => 2019-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16254266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/254266
Method for interface initialization using bus turn-around Jan 21, 2019 Issued
Array ( [id] => 14543437 [patent_doc_number] => 20190207340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => PROCESSING METHOD, PROCESSING APPARATUS, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/238332 [patent_app_country] => US [patent_app_date] => 2019-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16238332 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/238332
Processing method, processing apparatus, and electronic device Jan 1, 2019 Issued
Array ( [id] => 14220645 [patent_doc_number] => 20190122707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => APPARATUSES AND METHODS FOR STORING AND WRITING MULTIPLE PARAMETER CODES FOR MEMORY OPERATING PARAMETERS [patent_app_type] => utility [patent_app_number] => 16/222806 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/222806
Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters Dec 16, 2018 Issued
Array ( [id] => 15517135 [patent_doc_number] => 10565155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Distributed multi-die protocol application interface [patent_app_type] => utility [patent_app_number] => 16/208238 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4787 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208238 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/208238
Distributed multi-die protocol application interface Dec 2, 2018 Issued
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