Kamini S. Shah

Array ( [id] => 13580113 [patent_doc_number] => 20180341605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => PROGRAMMING INTERRUPTION MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/054189 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15638301 [patent_doc_number] => 10592144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Storage system fabric with multichannel compute complex [patent_app_type] => utility [patent_app_number] => 16/054980 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 12069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15440261 [patent_doc_number] => 20200034314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => Composable Serial Console and KVM with Remote Accessibility [patent_app_type] => utility [patent_app_number] => 16/048539 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15919703 [patent_doc_number] => 10657091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Speculative execution in a distributed streaming system [patent_app_type] => utility [patent_app_number] => 16/046760 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15284727 [patent_doc_number] => 10515028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Reference voltage calibration using a qualified weighted average [patent_app_type] => utility [patent_app_number] => 16/030794 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17744107 [patent_doc_number] => 11392174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Docking apparatus communication [patent_app_type] => utility [patent_app_number] => 17/042469 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5168 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17042469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14298941 [patent_doc_number] => 10289597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Devices, systems, and methods of reducing chip select [patent_app_type] => utility [patent_app_number] => 15/975637 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15317005 [patent_doc_number] => 10523223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Phase-locked loop circuit calibration method, memory storage device and connection interface circuit [patent_app_type] => utility [patent_app_number] => 15/973539 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6668 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15973539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15198131 [patent_doc_number] => 10496560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Component location identification and controls [patent_app_type] => utility [patent_app_number] => 15/971246 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4677 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18189762 [patent_doc_number] => 11580353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Neural network processor for handling differing datatypes [patent_app_type] => utility [patent_app_number] => 15/971868 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15545281 [patent_doc_number] => 10572422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Devices and methods for prioritizing transmission of events on serial communication links [patent_app_type] => utility [patent_app_number] => 15/970677 [patent_app_country] => US [patent_app_date] => 2018-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 11482 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15970677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16248335 [patent_doc_number] => 10747695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Methods of performing multiple data bus inversion (DBI) and memory devices performing the methods [patent_app_type] => utility [patent_app_number] => 15/969797 [patent_app_country] => US [patent_app_date] => 2018-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 41 [patent_no_of_words] => 17136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15090139 [patent_doc_number] => 20190339880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => DATA STORAGE DEVICE WITH SELECTIVE CONNECTION TO NON-VOLATILE MEMORIES [patent_app_type] => utility [patent_app_number] => 15/969278 [patent_app_country] => US [patent_app_date] => 2018-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15373589 [patent_doc_number] => 10528513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-07 [patent_title] => Circuit for and method of providing a programmable connector of an integrated circuit device [patent_app_type] => utility [patent_app_number] => 15/967473 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 8336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14076949 [patent_doc_number] => 20190087362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => STORAGE DEVICE COMMUNICATING WITH HOST ACCORDING TO MULTICAST COMMUNICATION PROTOCOL AND COMMUNICATION METHOD OF HOST [patent_app_type] => utility [patent_app_number] => 15/964737 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15043121 [patent_doc_number] => 20190332565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => System and Method of Managing Signals in Information Handling Systems [patent_app_type] => utility [patent_app_number] => 15/963739 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15963739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15027855 [patent_doc_number] => 20190324932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => PROVIDING INTERRUPT SERVICE ROUTINE (ISR) PREFETCHING IN MULTICORE PROCESSOR-BASED SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/958438 [patent_app_country] => US [patent_app_date] => 2018-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15958438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13334443 [patent_doc_number] => 20180218759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => DRAM DATA PATH SHARING VIA A SPLIT LOCAL DATA BUS [patent_app_type] => utility [patent_app_number] => 15/940811 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15940811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14250363 [patent_doc_number] => 10275382 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-30 [patent_title] => Modular apparatus and control method thereof [patent_app_type] => utility [patent_app_number] => 15/938495 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5681 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15938495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13320315 [patent_doc_number] => 20180211695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => APPARATUSES AND METHODS FOR STORING AND WRITING MULTIPLE PARAMETER CODES FOR MEMORY OPERATING PARAMETERS [patent_app_type] => utility [patent_app_number] => 15/933167 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -35 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933167 [rel_patent_id] =>[rel_patent_doc_number] =>)