
Kamini S. Shah
Supervisory Patent Examiner (ID: 9613, Phone: (571)272-2279 , Office: P/2123 )
| Most Active Art Unit | 2857 |
| Art Unit(s) | 2414, 2764, 2127, 2863, 2116, 2314, 2128, 2211, 2123, 2857, 2146, 2115, 2142 |
| Total Applications | 939 |
| Issued Applications | 692 |
| Pending Applications | 104 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13807317
[patent_doc_number] => 10180925
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-15
[patent_title] => Integrated circuit with pin level access to IO pins
[patent_app_type] => utility
[patent_app_number] => 15/081944
[patent_app_country] => US
[patent_app_date] => 2016-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 6013
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 396
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15081944
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/081944 | Integrated circuit with pin level access to IO pins | Mar 27, 2016 | Issued |
Array
(
[id] => 13273337
[patent_doc_number] => 10148761
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-04
[patent_title] => System-on-chip data security appliance and methods of operating the same
[patent_app_type] => utility
[patent_app_number] => 15/077519
[patent_app_country] => US
[patent_app_date] => 2016-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7110
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15077519
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/077519 | System-on-chip data security appliance and methods of operating the same | Mar 21, 2016 | Issued |
Array
(
[id] => 11359053
[patent_doc_number] => 09535706
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-03
[patent_title] => 'Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction'
[patent_app_type] => utility
[patent_app_number] => 15/077093
[patent_app_country] => US
[patent_app_date] => 2016-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 26
[patent_no_of_words] => 19422
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15077093
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/077093 | Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction | Mar 21, 2016 | Issued |
Array
(
[id] => 13273337
[patent_doc_number] => 10148761
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-04
[patent_title] => System-on-chip data security appliance and methods of operating the same
[patent_app_type] => utility
[patent_app_number] => 15/077519
[patent_app_country] => US
[patent_app_date] => 2016-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7110
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15077519
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/077519 | System-on-chip data security appliance and methods of operating the same | Mar 21, 2016 | Issued |
Array
(
[id] => 11665290
[patent_doc_number] => 20170154009
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-01
[patent_title] => 'METHOD FOR INTERFACE INITIALIZATION USING BUS TURN-AROUND'
[patent_app_type] => utility
[patent_app_number] => 15/070481
[patent_app_country] => US
[patent_app_date] => 2016-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5833
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15070481
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/070481 | Method for interface initialization using bus turn-around | Mar 14, 2016 | Issued |
Array
(
[id] => 11431061
[patent_doc_number] => 09569379
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-02-14
[patent_title] => 'Method for burning data into tire pressure monitoring device'
[patent_app_type] => utility
[patent_app_number] => 15/066844
[patent_app_country] => US
[patent_app_date] => 2016-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3537
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 699
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15066844
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/066844 | Method for burning data into tire pressure monitoring device | Mar 9, 2016 | Issued |
Array
(
[id] => 10994328
[patent_doc_number] => 20160191274
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-30
[patent_title] => 'METHOD AND APPARATUS FOR MINIMIZING WITHIN-DIE VARIATIONS IN PERFORMANCE PARAMETERS OF A PROCESSOR'
[patent_app_type] => utility
[patent_app_number] => 15/064146
[patent_app_country] => US
[patent_app_date] => 2016-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5751
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15064146
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/064146 | Method and apparatus for minimizing within-die variations in performance parameters of a processor | Mar 7, 2016 | Issued |
Array
(
[id] => 17492311
[patent_doc_number] => 11281614
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-22
[patent_title] => Static address allocation by passive electronics
[patent_app_type] => utility
[patent_app_number] => 15/061587
[patent_app_country] => US
[patent_app_date] => 2016-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 14954
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15061587
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/061587 | Static address allocation by passive electronics | Mar 3, 2016 | Issued |
Array
(
[id] => 11693267
[patent_doc_number] => 20170168984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-15
[patent_title] => 'DYNAMIC CLOCK LANE ASSIGNMENT FOR INCREASED PERFORMANCE AND SECURITY'
[patent_app_type] => utility
[patent_app_number] => 15/061045
[patent_app_country] => US
[patent_app_date] => 2016-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10282
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15061045
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/061045 | Dynamic clock lane assignment for increased performance and security | Mar 3, 2016 | Issued |
Array
(
[id] => 14364661
[patent_doc_number] => 10303636
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-28
[patent_title] => Routing paging packets in a system-on-a-chip base station architecture
[patent_app_type] => utility
[patent_app_number] => 15/056062
[patent_app_country] => US
[patent_app_date] => 2016-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 6601
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15056062
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/056062 | Routing paging packets in a system-on-a-chip base station architecture | Feb 28, 2016 | Issued |
Array
(
[id] => 14202285
[patent_doc_number] => 10268258
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-23
[patent_title] => Storage device having a serial communication port
[patent_app_type] => utility
[patent_app_number] => 15/057026
[patent_app_country] => US
[patent_app_date] => 2016-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4807
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15057026
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/057026 | Storage device having a serial communication port | Feb 28, 2016 | Issued |
Array
(
[id] => 12351852
[patent_doc_number] => 09952792
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-24
[patent_title] => Methods, systems, and computer readable media for storage device workload detection using power consumption
[patent_app_type] => utility
[patent_app_number] => 15/051254
[patent_app_country] => US
[patent_app_date] => 2016-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3275
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051254
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/051254 | Methods, systems, and computer readable media for storage device workload detection using power consumption | Feb 22, 2016 | Issued |
Array
(
[id] => 12551490
[patent_doc_number] => 10013379
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-03
[patent_title] => Auto-addressing of communication nodes
[patent_app_type] => utility
[patent_app_number] => 15/048354
[patent_app_country] => US
[patent_app_date] => 2016-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3770
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15048354
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/048354 | Auto-addressing of communication nodes | Feb 18, 2016 | Issued |
Array
(
[id] => 10786110
[patent_doc_number] => 20160132266
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-12
[patent_title] => 'METHODS AND APPARATUS TO MANAGE WORKLOAD MEMORY ALLOCATION'
[patent_app_type] => utility
[patent_app_number] => 14/982060
[patent_app_country] => US
[patent_app_date] => 2015-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8151
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14982060
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/982060 | Methods and apparatus to manage workload memory allocation | Dec 28, 2015 | Issued |
Array
(
[id] => 10999193
[patent_doc_number] => 20160196139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-07
[patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A SHUFFLE AND OPERATION (SHUFFLE-OP)'
[patent_app_type] => utility
[patent_app_number] => 14/981885
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 18524
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14981885
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/981885 | Systems, apparatuses, and methods for performing a shuffle and operation (Shuffle-Op) | Dec 27, 2015 | Issued |
Array
(
[id] => 14669491
[patent_doc_number] => 10372647
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-06
[patent_title] => Exascale fabric time synchronization
[patent_app_type] => utility
[patent_app_number] => 14/977773
[patent_app_country] => US
[patent_app_date] => 2015-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 18
[patent_no_of_words] => 13064
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977773
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/977773 | Exascale fabric time synchronization | Dec 21, 2015 | Issued |
Array
(
[id] => 14364645
[patent_doc_number] => 10303628
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-28
[patent_title] => Reordering responses in a high performance on-chip network
[patent_app_type] => utility
[patent_app_number] => 14/976620
[patent_app_country] => US
[patent_app_date] => 2015-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 14323
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 368
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14976620
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/976620 | Reordering responses in a high performance on-chip network | Dec 20, 2015 | Issued |
Array
(
[id] => 14766681
[patent_doc_number] => 10394737
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-08-27
[patent_title] => Multichip package with protocol-configurable data paths
[patent_app_type] => utility
[patent_app_number] => 14/975270
[patent_app_country] => US
[patent_app_date] => 2015-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 5699
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975270
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/975270 | Multichip package with protocol-configurable data paths | Dec 17, 2015 | Issued |
Array
(
[id] => 14330921
[patent_doc_number] => 10296479
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-05-21
[patent_title] => Scalable circuitry and method for control insertion
[patent_app_type] => utility
[patent_app_number] => 14/975370
[patent_app_country] => US
[patent_app_date] => 2015-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 5676
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975370
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/975370 | Scalable circuitry and method for control insertion | Dec 17, 2015 | Issued |
Array
(
[id] => 12293424
[patent_doc_number] => 09934827
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-03
[patent_title] => DRAM data path sharing via a split local data bus
[patent_app_type] => utility
[patent_app_number] => 14/975298
[patent_app_country] => US
[patent_app_date] => 2015-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7037
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975298
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/975298 | DRAM data path sharing via a split local data bus | Dec 17, 2015 | Issued |