Search

Kamini S. Shah

Supervisory Patent Examiner (ID: 9613, Phone: (571)272-2279 , Office: P/2123 )

Most Active Art Unit
2857
Art Unit(s)
2414, 2764, 2127, 2863, 2116, 2314, 2128, 2211, 2123, 2857, 2146, 2115, 2142
Total Applications
939
Issued Applications
692
Pending Applications
104
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11709409 [patent_doc_number] => 20170177909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'METHOD AND APPARATUS FOR PROTECTING A PCI DEVICE CONTROLLER FROM MASQUERADE ATTACKS BY MALWARE' [patent_app_type] => utility [patent_app_number] => 14/973271 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8130 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973271 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973271
Method and apparatus for protecting a PCI device controller from masquerade attacks by malware Dec 16, 2015 Issued
Array ( [id] => 12373026 [patent_doc_number] => 09959227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-01 [patent_title] => Reducing input/output latency using a direct memory access (DMA) engine [patent_app_type] => utility [patent_app_number] => 14/971759 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14971759 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/971759
Reducing input/output latency using a direct memory access (DMA) engine Dec 15, 2015 Issued
Array ( [id] => 12332031 [patent_doc_number] => 09946671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-17 [patent_title] => Methods and systems for processing read and write requests [patent_app_type] => utility [patent_app_number] => 14/969950 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969950 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/969950
Methods and systems for processing read and write requests Dec 14, 2015 Issued
Array ( [id] => 11693266 [patent_doc_number] => 20170168983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'DYNAMIC CLOCK LANE ASSIGNMENT FOR INCREASED PERFORMANCE AND SECURITY' [patent_app_type] => utility [patent_app_number] => 14/968166 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10399 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968166 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968166
Dynamic clock lane assignment for increased performance and security Dec 13, 2015 Issued
Array ( [id] => 12393576 [patent_doc_number] => 09965441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Adaptive coalescing of remote direct memory access acknowledgements based on I/O characteristics [patent_app_type] => utility [patent_app_number] => 14/965736 [patent_app_country] => US [patent_app_date] => 2015-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11530 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14965736 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/965736
Adaptive coalescing of remote direct memory access acknowledgements based on I/O characteristics Dec 9, 2015 Issued
Array ( [id] => 17557972 [patent_doc_number] => 11314676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Apparatus and method for buffered interconnect [patent_app_type] => utility [patent_app_number] => 14/944340 [patent_app_country] => US [patent_app_date] => 2015-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5021 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14944340 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/944340
Apparatus and method for buffered interconnect Nov 17, 2015 Issued
Array ( [id] => 10716740 [patent_doc_number] => 20160062887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'FLEXIBLE ARBITRATION SCHEME FOR MULTI ENDPOINT ATOMIC ACCESSES IN MULTICORE SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/937945 [patent_app_country] => US [patent_app_date] => 2015-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1813 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14937945 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/937945
Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems Nov 10, 2015 Issued
Array ( [id] => 10680321 [patent_doc_number] => 20160026466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'INSTRUCTION SET FOR SUPPORTING WIDE SCALAR PATTERN MATCHES' [patent_app_type] => utility [patent_app_number] => 14/876432 [patent_app_country] => US [patent_app_date] => 2015-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 20090 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14876432 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/876432
Instruction set for supporting wide scalar pattern matches Oct 5, 2015 Issued
Array ( [id] => 10672856 [patent_doc_number] => 20160019001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'THICK AND THIN DATA VOLUME MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 14/866531 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10395 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14866531 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/866531
Thick and thin data volume management Sep 24, 2015 Issued
Array ( [id] => 11042666 [patent_doc_number] => 20160239623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'MEDICAL DEVICE COMPRISING MULTI-FUNCTIONAL SOCKET' [patent_app_type] => utility [patent_app_number] => 14/850566 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5579 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850566 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/850566
MEDICAL DEVICE COMPRISING MULTI-FUNCTIONAL SOCKET Sep 9, 2015 Abandoned
Array ( [id] => 13110303 [patent_doc_number] => 10073805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Virtual expansion ROM in a PCIe environment [patent_app_type] => utility [patent_app_number] => 14/845026 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5153 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845026 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/845026
Virtual expansion ROM in a PCIe environment Sep 2, 2015 Issued
Array ( [id] => 11494453 [patent_doc_number] => 20170068638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'DISTRIBUTED MULTI-DIE PROTOCOL APPLICATION INTERFACE' [patent_app_type] => utility [patent_app_number] => 14/844920 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5118 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844920 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/844920
Distributed multi-die protocol application interface Sep 2, 2015 Issued
Array ( [id] => 11070081 [patent_doc_number] => 20160267045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/844089 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10907 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844089 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/844089
Semiconductor storage device Sep 2, 2015 Issued
Array ( [id] => 14298903 [patent_doc_number] => 10289578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Per-DRAM and per-buffer addressability shadow registers and write-back functionality [patent_app_type] => utility [patent_app_number] => 14/842175 [patent_app_country] => US [patent_app_date] => 2015-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14842175 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/842175
Per-DRAM and per-buffer addressability shadow registers and write-back functionality Aug 31, 2015 Issued
Array ( [id] => 10739557 [patent_doc_number] => 20160085708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'MULTI-LEVEL SCALABLE SWITCH ARCHITECTURE FOR STORAGE APPLIANCE' [patent_app_type] => utility [patent_app_number] => 14/842804 [patent_app_country] => US [patent_app_date] => 2015-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2084 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14842804 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/842804
MULTI-LEVEL SCALABLE SWITCH ARCHITECTURE FOR STORAGE APPLIANCE Aug 31, 2015 Abandoned
Array ( [id] => 11780683 [patent_doc_number] => 09389864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Data processing device and method, and processor unit of same' [patent_app_type] => utility [patent_app_number] => 14/841918 [patent_app_country] => US [patent_app_date] => 2015-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7979 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14841918 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/841918
Data processing device and method, and processor unit of same Aug 31, 2015 Issued
Array ( [id] => 17744448 [patent_doc_number] => 11392517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Access control method, bus system, and semiconductor device [patent_app_type] => utility [patent_app_number] => 15/502751 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 12325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15502751 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/502751
Access control method, bus system, and semiconductor device Aug 30, 2015 Issued
Array ( [id] => 12146697 [patent_doc_number] => 09880950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Dynamically addressable master-slave system and method for dynamically addressing slave units' [patent_app_type] => utility [patent_app_number] => 14/840151 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3696 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14840151 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/840151
Dynamically addressable master-slave system and method for dynamically addressing slave units Aug 30, 2015 Issued
Array ( [id] => 11830777 [patent_doc_number] => 09727519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Emulating bi-directional bus communication using separate unidirectional channels' [patent_app_type] => utility [patent_app_number] => 14/835797 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3678 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835797 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/835797
Emulating bi-directional bus communication using separate unidirectional channels Aug 25, 2015 Issued
Array ( [id] => 11459015 [patent_doc_number] => 20170052921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'INTEGRATED INPUT/OUTPUT CONNECTOR' [patent_app_type] => utility [patent_app_number] => 14/831169 [patent_app_country] => US [patent_app_date] => 2015-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1515 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14831169 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/831169
Integrated input/output connector Aug 19, 2015 Issued
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