Search

Kamran Afshar

Supervisory Patent Examiner (ID: 4027, Phone: (571)272-7796 , Office: P/2646 )

Most Active Art Unit
2617
Art Unit(s)
2125, 2682, 2681, 2646, 2617
Total Applications
712
Issued Applications
512
Pending Applications
77
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6285020 [patent_doc_number] => 20020053718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Power semiconductor device' [patent_app_type] => new [patent_app_number] => 09/883477 [patent_app_country] => US [patent_app_date] => 2001-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1790 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053718.pdf [firstpage_image] =>[orig_patent_app_number] => 09883477 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/883477
Power semiconductor component having a PN junction with a low area edge termination Jun 17, 2001 Issued
Array ( [id] => 6986918 [patent_doc_number] => 20010036750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Dual damascene anti-fuse with via before wire' [patent_app_type] => new [patent_app_number] => 09/873537 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3527 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036750.pdf [firstpage_image] =>[orig_patent_app_number] => 09873537 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873537
Dual damascene anti-fuse with via before wire Jun 3, 2001 Issued
Array ( [id] => 6384988 [patent_doc_number] => 20020179957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Structure and method for fabricating high Q varactor diodes' [patent_app_type] => new [patent_app_number] => 09/865447 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15621 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20020179957.pdf [firstpage_image] =>[orig_patent_app_number] => 09865447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865447
Structure and method for fabricating high Q varactor diodes May 28, 2001 Abandoned
Array ( [id] => 6900813 [patent_doc_number] => 20010022396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Fan-out semiconductor chip assembly' [patent_app_type] => new [patent_app_number] => 09/863927 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8801 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20010022396.pdf [firstpage_image] =>[orig_patent_app_number] => 09863927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863927
Fan-out semiconductor chip assembly May 22, 2001 Abandoned
Array ( [id] => 1169920 [patent_doc_number] => 06756676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/863737 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4045 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756676.pdf [firstpage_image] =>[orig_patent_app_number] => 09863737 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863737
Semiconductor device and method of manufacturing the same May 22, 2001 Issued
Array ( [id] => 6933418 [patent_doc_number] => 20010054762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 09/863077 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7672 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054762.pdf [firstpage_image] =>[orig_patent_app_number] => 09863077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863077
Semiconductor device and method of fabricating the same May 22, 2001 Abandoned
Array ( [id] => 6290396 [patent_doc_number] => 20020055224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays' [patent_app_type] => new [patent_app_number] => 09/862827 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6251 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055224.pdf [firstpage_image] =>[orig_patent_app_number] => 09862827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862827
Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays May 21, 2001 Issued
Array ( [id] => 1229997 [patent_doc_number] => 06696752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Encapsulated semiconductor device with flash-proof structure' [patent_app_type] => B2 [patent_app_number] => 09/862347 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3664 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696752.pdf [firstpage_image] =>[orig_patent_app_number] => 09862347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862347
Encapsulated semiconductor device with flash-proof structure May 21, 2001 Issued
Array ( [id] => 5870666 [patent_doc_number] => 20020047185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Lead frame tooling design for bleed barrier groove' [patent_app_type] => new [patent_app_number] => 09/862067 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3351 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20020047185.pdf [firstpage_image] =>[orig_patent_app_number] => 09862067 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862067
Lead frame tooling design for bleed barrier groove May 20, 2001 Abandoned
Array ( [id] => 1352436 [patent_doc_number] => 06583499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Quad flat non-leaded package and leadframe for use in a quad flat non-leaded package' [patent_app_type] => B2 [patent_app_number] => 09/861757 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2585 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583499.pdf [firstpage_image] =>[orig_patent_app_number] => 09861757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/861757
Quad flat non-leaded package and leadframe for use in a quad flat non-leaded package May 20, 2001 Issued
Array ( [id] => 6107173 [patent_doc_number] => 20020171125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Organic semiconductor devices with short channels' [patent_app_type] => new [patent_app_number] => 09/860107 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3188 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20020171125.pdf [firstpage_image] =>[orig_patent_app_number] => 09860107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/860107
Organic semiconductor devices with short channels May 16, 2001 Abandoned
Array ( [id] => 6888524 [patent_doc_number] => 20010023979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Method and system for dicing wafers, and semiconductor structures incorporating the products thereof' [patent_app_type] => new [patent_app_number] => 09/855617 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4778 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023979.pdf [firstpage_image] =>[orig_patent_app_number] => 09855617 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/855617
Semiconductor structure and package including a chip having chamfered edges May 14, 2001 Issued
Array ( [id] => 5870697 [patent_doc_number] => 20020047199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Semiconductor device, manufacturing method of semiconductor device, stack type semiconductor device, and manufacturing method of stack type semiconductor device' [patent_app_type] => new [patent_app_number] => 09/852847 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6717 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20020047199.pdf [firstpage_image] =>[orig_patent_app_number] => 09852847 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/852847
Semiconductor device, manufacturing method of semiconductor device, stack type semiconductor device, and manufacturing method of stack type semiconductor device May 10, 2001 Issued
Array ( [id] => 687879 [patent_doc_number] => 07078819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Microelectronic packages with elongated solder interconnections' [patent_app_type] => utility [patent_app_number] => 09/854269 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 7471 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078819.pdf [firstpage_image] =>[orig_patent_app_number] => 09854269 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/854269
Microelectronic packages with elongated solder interconnections May 10, 2001 Issued
Array ( [id] => 6897498 [patent_doc_number] => 20010045663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Semiconductor circuit device and method for manufacturing thereof' [patent_app_type] => new [patent_app_number] => 09/851987 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5208 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20010045663.pdf [firstpage_image] =>[orig_patent_app_number] => 09851987 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/851987
Semiconductor circuit device and method for manufacturing thereof May 9, 2001 Abandoned
Array ( [id] => 1400290 [patent_doc_number] => 06545357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Metal nitride barrier layer and electroplating seed layer with the same metal as the metal nitride layer' [patent_app_type] => B2 [patent_app_number] => 09/853451 [patent_app_country] => US [patent_app_date] => 2001-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4642 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545357.pdf [firstpage_image] =>[orig_patent_app_number] => 09853451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/853451
Metal nitride barrier layer and electroplating seed layer with the same metal as the metal nitride layer May 8, 2001 Issued
Array ( [id] => 6713864 [patent_doc_number] => 20030025212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Semiconductor LED flip-chip with high reflectivity dielectric coating on the mesa' [patent_app_type] => new [patent_app_number] => 09/852857 [patent_app_country] => US [patent_app_date] => 2001-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3962 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20030025212.pdf [firstpage_image] =>[orig_patent_app_number] => 09852857 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/852857
Semiconductor LED flip-chip with high reflectivity dielectric coating on the mesa May 8, 2001 Issued
Array ( [id] => 440245 [patent_doc_number] => 07259448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Die-up ball grid array package with a heat spreader and method for making the same' [patent_app_type] => utility [patent_app_number] => 09/849537 [patent_app_country] => US [patent_app_date] => 2001-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6703 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/259/07259448.pdf [firstpage_image] =>[orig_patent_app_number] => 09849537 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/849537
Die-up ball grid array package with a heat spreader and method for making the same May 6, 2001 Issued
Array ( [id] => 1086519 [patent_doc_number] => 06831346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Buried layer substrate isolation in integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/849047 [patent_app_country] => US [patent_app_date] => 2001-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5777 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831346.pdf [firstpage_image] =>[orig_patent_app_number] => 09849047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/849047
Buried layer substrate isolation in integrated circuits May 3, 2001 Issued
Array ( [id] => 1400040 [patent_doc_number] => 06545343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Hybrid frame with lead-lock tape' [patent_app_type] => B2 [patent_app_number] => 09/847689 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3418 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545343.pdf [firstpage_image] =>[orig_patent_app_number] => 09847689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847689
Hybrid frame with lead-lock tape May 1, 2001 Issued
Menu