Search

Kannan Shanmugasundaram

Examiner (ID: 10064, Phone: (571)270-7763 , Office: P/2158 )

Most Active Art Unit
2158
Art Unit(s)
4152, 2158, 2168
Total Applications
619
Issued Applications
408
Pending Applications
63
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19250784 [patent_doc_number] => 20240201774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => STORAGE CONTROLLER, STORAGE DEVICE INCLUDING THE SAME, AND OPERATION METHOD OF STORAGE CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/589263 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589263 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589263
Storage controller, storage device including the same, and operation method of storage controller Feb 26, 2024 Issued
Array ( [id] => 20195211 [patent_doc_number] => 20250271921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => SSD Power Management With Hybrid PCIe Link State Method [patent_app_type] => utility [patent_app_number] => 18/588236 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588236 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588236
SSD Power Management With Hybrid PCIe Link State Method Feb 26, 2024 Pending
Array ( [id] => 19434388 [patent_doc_number] => 20240302886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SYSTEMS AND METHODS OF ESTIMATING POWER FOR THERMAL MANAGEMENT IN POWER-CONSTRAINED DEVICES [patent_app_type] => utility [patent_app_number] => 18/427152 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/427152
Systems and methods of estimating power for thermal management in power-constrained devices Jan 29, 2024 Issued
Array ( [id] => 20070465 [patent_doc_number] => 20250208687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => POWER REDUCTION IN AN ARRAY OF DATA PROCESSING ENGINES [patent_app_type] => utility [patent_app_number] => 18/394706 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18394706 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/394706
POWER REDUCTION IN AN ARRAY OF DATA PROCESSING ENGINES Dec 21, 2023 Pending
Array ( [id] => 20061377 [patent_doc_number] => 20250199599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => PROCESSOR LOW POWER MODE ENHANCEMENT [patent_app_type] => utility [patent_app_number] => 18/539201 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539201 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/539201
PROCESSOR LOW POWER MODE ENHANCEMENT Dec 12, 2023 Pending
Array ( [id] => 19084552 [patent_doc_number] => 20240111353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING [patent_app_type] => utility [patent_app_number] => 18/538116 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538116 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538116
CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING Dec 12, 2023 Pending
Array ( [id] => 19204507 [patent_doc_number] => 20240176406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => Preemptive Processor Power Supply Regulator Feedback Modulation to Mitigate Voltage Overshoot and Undershoot [patent_app_type] => utility [patent_app_number] => 18/524991 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524991 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524991
Preemptive Processor Power Supply Regulator Feedback Modulation to Mitigate Voltage Overshoot and Undershoot Nov 29, 2023 Pending
Array ( [id] => 19204507 [patent_doc_number] => 20240176406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => Preemptive Processor Power Supply Regulator Feedback Modulation to Mitigate Voltage Overshoot and Undershoot [patent_app_type] => utility [patent_app_number] => 18/524991 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524991 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524991
Preemptive Processor Power Supply Regulator Feedback Modulation to Mitigate Voltage Overshoot and Undershoot Nov 29, 2023 Pending
Array ( [id] => 20257554 [patent_doc_number] => 12429904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Heterogeneous computing systems and methods for clock synchronization [patent_app_type] => utility [patent_app_number] => 18/522071 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522071 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522071
Heterogeneous computing systems and methods for clock synchronization Nov 27, 2023 Issued
Array ( [id] => 19204509 [patent_doc_number] => 20240176408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => Standby modes to minimise consumption and startup time [patent_app_type] => utility [patent_app_number] => 18/521588 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521588 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521588
Standby modes to minimise consumption and startup time Nov 27, 2023 Pending
Array ( [id] => 19189626 [patent_doc_number] => 20240168539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => ABRUPT SHUTDOWN AND ABRUPT POWER LOSS MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/511408 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511408 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/511408
ABRUPT SHUTDOWN AND ABRUPT POWER LOSS MANAGEMENT Nov 15, 2023 Pending
Array ( [id] => 19885534 [patent_doc_number] => 12271247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => System on chip controlling memory power using handshake process and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/500563 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18500563 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/500563
System on chip controlling memory power using handshake process and operating method thereof Nov 1, 2023 Issued
Array ( [id] => 19267322 [patent_doc_number] => 20240211024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => WAKE-UP MECHANISM CONTROLLING METHOD, ELECTRONIC SYSTEM, NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/488992 [patent_app_country] => US [patent_app_date] => 2023-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/488992
Wake-up mechanism controlling method, electronic system, non-transitory computer readable storage medium Oct 16, 2023 Issued
Array ( [id] => 19267322 [patent_doc_number] => 20240211024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => WAKE-UP MECHANISM CONTROLLING METHOD, ELECTRONIC SYSTEM, NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/488992 [patent_app_country] => US [patent_app_date] => 2023-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/488992
Wake-up mechanism controlling method, electronic system, non-transitory computer readable storage medium Oct 16, 2023 Issued
Array ( [id] => 19334081 [patent_doc_number] => 20240248511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => CLOCK DRIVER, OPERATING METHOD THEREOF, MEMORY DEVICE INCLUDING CLOCK DRIVER, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/476508 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18476508 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/476508
Clock driver, operating method thereof, memory device including clock driver, and memory system Sep 27, 2023 Issued
Array ( [id] => 19595615 [patent_doc_number] => 12153456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Dynamic current scaling of a regulator [patent_app_type] => utility [patent_app_number] => 18/475678 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475678
Dynamic current scaling of a regulator Sep 26, 2023 Issued
Array ( [id] => 18896961 [patent_doc_number] => 20240012446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/471844 [patent_app_country] => US [patent_app_date] => 2023-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18471844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/471844
Semiconductor device Sep 20, 2023 Issued
Array ( [id] => 19450767 [patent_doc_number] => 20240310897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MULTI-NODE COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/472169 [patent_app_country] => US [patent_app_date] => 2023-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472169 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/472169
MULTI-NODE COMPUTING SYSTEM Sep 20, 2023 Pending
Array ( [id] => 19848591 [patent_doc_number] => 20250093942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => PROCESSORS INCLUDING POWER CONTROL CIRCUITS TO REDUCE A NO-LOAD VOLTAGE TO SAVE POWER AND INCREASE LONGEVITY AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/469890 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469890 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/469890
Processors including power control circuits to reduce a no-load voltage to save power and increase longevity and related methods Sep 18, 2023 Issued
Array ( [id] => 19848591 [patent_doc_number] => 20250093942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => PROCESSORS INCLUDING POWER CONTROL CIRCUITS TO REDUCE A NO-LOAD VOLTAGE TO SAVE POWER AND INCREASE LONGEVITY AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/469890 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469890 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/469890
Processors including power control circuits to reduce a no-load voltage to save power and increase longevity and related methods Sep 18, 2023 Issued
Menu